stwcx. (Store Word Conditional Indexed) instruction

Purpose

Used in conjunction with a preceding lwarx instruction to emulate a read-modify-write operation on a specified memory location.

Note: The stwcx. instruction is supported only in the PowerPC® architecture.

Syntax

Description

The stwcx. and lwarx instructions are primitive, or simple, instructions used to perform a read-modify-write operation to storage. If the store is performed, the use of the stwcx. and lwarx instructions ensures that no other processor or mechanism has modified the target memory location between the time the lwarx instruction is executed and the time the stwcx. instruction completes.

Consider the following when using the stwcx. instruction:

• If general-purpose register (GPR) RA is 0, the effective address (EA) is the content of GPR RB, otherwise EA is the sum of the content of GPR RA plus the content of GPR RB.
• If the reservation created by a lwarx instruction exists, the content of GPR RS is stored into the word in storage and addressed by EA and the reservation is cleared. Otherwise, the storage is not altered.
• If the store is performed, bits 0-2 of Condition Register Field 0 are set to 0b001, otherwise, they are set to 0b000. The SO bit of the XER is copied to bit 4 of Condition Register Field 0.

The stwcx. instruction has one syntax form and does not affect the Fixed-Point Exception Register. If the EA is not a multiple of 4, the results are undefined.

Parameters

Examples

1. The following code performs a "Fetch and Store" by atomically loading and replacing a word in storage:

   
   # Assume that GPR 4 contains the new value to be stored.
   # Assume that GPR 3 contains the address of the word
   # to be loaded and replaced.
   loop:   lwarx   r5,0,r3          # Load and reserve
           stwcx.  r4,0,r3          # Store new value if still
                                    # reserved
           bne-    loop             # Loop if lost reservation
   # The new value is now in storage.
   # The old value is returned to GPR 4. 
   

2. The following code performs a "Compare and Swap" by atomically comparing a value in a register with a word in storage:

   
   # Assume that GPR 5 contains the new value to be stored after
   # a successful match.
   # Assume that GPR 3 contains the address of the word
   # to be tested.
   # Assume that GPR 4 contains the value to be compared against
   # the value in memory.
   loop:   lwarx   r6,0,r3          # Load and reserve
           cmpw    r4,r6            # Are the first two operands
                                    # equal?
           bne-    exit             # Skip if not equal
           stwcx.  r5,0,r3          # Store new value if still
                                    # reserved
           bne-    loop             # Loop if lost reservation
   exit:   mr      r4,r6            # Return value from storage
   # The old value is returned to GPR 4.
   # If a match was made, storage contains the new value.
   

   If the value in the register equals the word in storage, the value from a second register is stored in the word in storage. If they are unequal, the word from storage is loaded into the first register and the EQ bit of the Condition Register Field 0 is set to indicate the result of the comparison.