Appendix H value definitions

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Bits 0-5

These bits represent the opcode portion of the machine instruction.

Bits 6-30

These bits contain fields defined according to the values below. Note that many instructions also contain extended opcodes, which occupy some portion of the bits in this range. Refer to specific instructions to understand the format utilized.

Value Definition
/, //, /// Reserved/unused; nominally zero (0).
A Pseudonym for RA in some diagrams.
AA Absolute address bit.
  • 0 - The immediate field represents an address relative to the current instruction address..
  • 1 - The immediate field represents an absolute address.
B Pseudonym for RB in some diagrams.
BA Specifies source condition register bit for operation.
BB Specifies source condition register bit for operation.
BD Specifies a 14-bit value used as the branch displacement.
BF Specifies condition register field 0-7 which indicates the result of a compare.
BFA Specifies source condition register field for operation.
BI Specifies bit in condition register for condition comparison.
BO Specifies branch option field used in instruction.
BT Specifies target condition register bit where result of operation is stored.
D Specifies 16-bit two's-complement integer sign extended to 32 bits.
DS Specifies a 14-bit field used as an immediate value for the calculation of an effective address (EA).
FL1 Specifies field for optional data passing the SVC routine.
FL2 Specifies field for optional data passing the SVC routine.
FLM Specifies field mask.
FRA Specifies source floating-point register for operation.
FRB Specifies source floating-point register for operation.
FRC Specifies source floating-point register for operation.
FRS Specifies source floating-point register of stored data.
FRT Specifies target floating-point register for operation.
FXM Specifies field mask.
I Specifies source immediate value for operation.
L Must be set to 0 for the 32-bit subset architecture.
LEV Specifies the execution address.
LI Immediate field specifying a 24-bit signed two's complement integer that is concatenated on the right with 0b00 and sign-extended to 64 bits (32 bits in 32-bit implementations).
LK If LK=1, the effective address of the instruction following the branch instruction is place into the link register.
MB Specifies the begin value (bit number) of the mask for the operation.
ME Specifies the end value (bit number) of the mask for the operation.
NB Specifies the byte count for the operation.
OE Specifies that the overflow bits in the Fixed-Point Exception register are affected if the operation results in overflow
RA Specifies the source general-purpose register for the operation.
RB Specifies the source general-purpose register for the operation.
RS Specifies the source general-purpose register for the operation.
RT Specifies the target general-purpose register where the operation is stored.
S Pseudonym for RS in some diagrams.
SA Documented in the svc instruction.
SH Specifies the (immediate) shift value for the operation.
SI Specifies the 16-bit signed integer for the operation.
SIMM 16-bit two's-complement value which will be sign-extended for comparison.
SPR Specifies the source special purpose register for the operation.
SR Specifies the source segment register for the operation.
ST Specifies the target segment register for the operation.
TO Specifies TO bits that are ANDed with compare results.
U Specifies source immediate value for operation.
UI Specifies 16-bit unsigned integer for operation.

Bit 31

Bit 31 is the record bit.

Value Definition
0 Does not update the condition register.
1 Updates the condition register to reflect the result of the operation.