mtfsb0 (Move to FPSCR Bit 0) instruction
Purpose
Sets a specified Floating-Point Status and Control Register bit to 0.
Syntax
Bits | Value |
---|---|
0 - 5 | 63 |
6 - 10 | BT |
11 - 15 | /// |
16 - 20 | /// |
21 - 30 | 70 |
31 | Rc |
Description
The mtfsb0 instruction sets the Floating-Point Status and Control Register bit specified by BT to 0.
The mtfsb0 instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.
Item | Description | ||
---|---|---|---|
Syntax Form | Fixed-Point Exception Register | Record Bit (Rc) | Condition Register Field 1 |
mtfsb0 | None | 0 | None |
mtfsb0. | None | 1 | FX, FEX, VX, OX |
The two syntax forms of the mtfsb0 instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.
Note: Bits 1-2 cannot be explicitly set or reset.
Parameters
Item | Description |
---|---|
BT | Specifies Floating-Point Status and Control Register bit set by operation. |
Examples
- The following code sets the Floating-Point Status
and Control Register Floating-Point Overflow Exception Bit (bit 3)
to 0:
mtfsb0 3 # Now bit 3 of the Floating-Point Status and Control # Register is 0.
- The following code sets the Floating-Point Status
and Control Register Floating-Point Overflow Exception Bit (bit 3)
to 0 and sets Condition Register Field 1 to reflect the result of
the operation:
mtfsb0. 3 # Now bit 3 of the Floating-Point Status and Control # Register is 0.