lhzu (Load Half and Zero with Update) instruction
Purpose
Loads a halfword of data from a specified location in memory into a general-purpose register, sets the remaining 16 bits of the general-purpose register to 0, and possibly places the address in another general-purpose register.
Syntax
| Bits | Value |
|---|---|
| 0 - 5 | 41 |
| 6 - 10 | RT |
| 11 - 15 | RA |
| 16 - 31 | D |
Description
The lhzu instruction loads a halfword of data from a specified location in memory, addressed by the effective address (EA), into bits 16-31 of the target general-purpose register (GPR) RT and sets bits 0-15 of GPR RT to 0.
If GPR RA is not 0, the EA is the sum of the contents of GPR RA and D, a 16-bit, signed two's complement integer sign-extended to 32 bits. If GPR RA is 0, then the EA is D.
If RA does not equal RT and RA does not equal 0, and the storage access does not cause an Alignment interrupt or a Data Storage interrupt, then the EA is placed into GPR RA.
The lhzu instruction has one syntax form and does not affect the Fixed-Point Exception Register or Condition Register Field 0.
Parameters
| Item | Description |
|---|---|
| RT | Specifies target general-purpose register where result of operation is stored. |
| D | 16-bit, signed two's complement integer sign-extended to 32 bits for EA calculation. |
| RA | Specifies source general-purpose register for EA calculation and possible address update. |
Examples
The following code loads a halfword of data into bits 16-31 of GPR 6, sets bits 0-15 of GPR 6 to 0, and stores the effective address in GPR 4:
.csect data[rw]
.short 0xffff
# Assume GPR 4 contains the address of csect data[rw].
.csect text[pr]
lhzu 6,0(4)
# GPR 6 now contains 0x0000 ffff.