fsub or fs (Floating Subtract) instruction

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Purpose

Subtracts one floating-point operand from another and places the result in a floating-point register.

Syntax

Bits Value
0-5 63
6-10 FRT
11-15 FRA
16-20 FRB
21-25 ///
26-30 20
31 Rc
PowerPC® 
fsub FRT, FRA, FRB
fsub. FRT, FRA, FRB
PowerPC® 
fs FRT, FRA, FRB
fs. FRT, FRA, FRB
Bits Value
0-5 59
6-10 FRT
11-15 FRA
16-20 FRB
21-25 ///
26-30 20
31 Rc
PowerPC® 
fsubs FRT, FRA, FRB
fsubs. FRT, FRA, FRB

Description

The fsub and fs instructions subtract the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRB from the 64-bit, double-precision floating-point operand in FPR FRA.

The fsubs instruction subtracts the 32-bit single-precision floating-point operand in FPR FRB from the 32-bit single-precision floating-point operand in FPR FRA.

The result is rounded under control of the Floating-Point Rounding Control Field RN of the Floating-Point Status and Control Register and is placed in the target FPR FRT.

The execution of the fsub instruction is identical to that of fadd, except that the contents of FPR FRB participate in the operation with bit 0 inverted.

The execution of the fs instruction is identical to that of fa, except that the contents of FPR FRB participate in the operation with bit 0 inverted.

The Floating-Point Result Flags Field of the Floating-Point Status and Control Register is set to the class and sign of the result, except for Invalid Operation Exceptions, when the Floating-Point Invalid Operation Exception Enable bit is 1.

The fsub, fsubs, and fs instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

Item Description
Syntax Form Floating-Point Status and Control Register Record Bit (Rc) Condition Register Field 1
fsub C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI 0 None
fsub. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI 1 FX,FEX,VX,OX
fsubs C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI 0 None
fsubs. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI 1 FX,FEX,VX,OX
fs C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI 0 None
fs. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN,VXISI 1 FX,FEX,VX,OX

All syntax forms of the fsub, fsubs, and fs instructions always affect the Floating-Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Parameters

Item Description
FRT Specifies target floating-point register for operation.
FRA Specifies source floating-point register for operation.
FRB Specifies source floating-point register for operation.

Examples

  1. The following code subtracts the contents of FPR 5 from the contents of FPR 4, places the result in FPR 6, and sets the Floating-Point Status and Control Register to reflect the result of the operation: 
    
# Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPSCR = 0.
fsub 6,4,5
# FPR 6 now contains 0xC054 2000 0000 0000.
# FPSCR now contains 0x0000 8000.
  2. The following code subtracts the contents of FPR 5 from the contents of FPR 4, places the result in FPR 6, and sets the Floating-Point Status and Control Register and Condition Register Field 1 to reflect the result of the operation: 
    
# Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPR 5 contains 0x400C 0000 0000 0000.
# Assume FPSCR = 0 and CR = 0.
fsub. 6,5,4
# FPR 6 now contains 0x4054 2000 0000 0000.
# FPSCR now contains 0x0000 4000.
# CR now contains 0x0000 0000.