fmsub or fms (Floating Multiply-Subtract) instruction

Purpose

Subtracts one floating-point operand from the result of multiplying two floating-point operands without an intermediate rounding operation.

Syntax

Description

The fmsub and fms instructions multiply the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRA by the 64-bit, double-precision floating-point operand in FPR FRC and subtract the 64-bit, double-precision floating-point operand in FPR FRB from the result of the multiplication.

The fmsubs instruction multiplies the 32-bit, single-precision floating-point operand in FPR FRA by the 32-bit, single-precision floating-point operand in FPR FRC and subtracts the 32-bit, single-precision floating-point operand in FPR FRB from the result of the multiplication.

The result is rounded under control of the Floating-Point Rounding Control Field RN of the Floating-Point Status and Control Register and is placed in the target FPR FRT.

Note: If an operand is a denormalized number, then it is prenormalized before the operation is begun.

The Floating-Point Result Flags Field of the Floating-Point Status and Control Register is set to the class and sign of the result, except for Invalid Operation Exceptions, when the Floating-Point Invalid Operation Exception Enable bit is 1.

The fmsub, fmsubs, and fms instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

All syntax forms of the fmsub, fmsubs, and fms instructions always affect the Floating-Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Parameters

Examples

1. The following code multiplies the contents of FPR 4 and FPR 5, subtracts the contents of FPR 7 from the product of the multiplication, places the result in FPR 6, and sets the Floating-Point Status and Control Register to reflect the result of the operation:

   
   # Assume FPR 4 contains 0xC053 4000 0000 0000.
   # Assume FPR 5 contains 0x400C 0000 0000 0000.
   # Assume FPR 7 contains 0x3DE2 6AB4 B33c 110A.
   # Assume FPSCR = 0.
   fmsub 6,4,5,7
   # FPR 6 now contains 0xC070 D800 0000 0935.
   # FPSCR now contains 0x8202 8000.
   

2. The following code multiplies the contents of FPR 4 and FPR 5, subtracts the contents of FPR 7 from the product of the multiplication, places the result in FPR 6, and sets the Floating-Point Status and Control Register and Condition Register Field 1 to reflect the result of the operation:

   
   # Assume FPR 4 contains 0xC053 4000 0000 0000.
   # Assume FPR 5 contains 0x400C 0000 0000 0000.
   # Assume FPR 7 contains 0x3DE2 6AB4 B33c 110A.
   # Assume FPSCR = 0 and CR = 0.
   fmsub. 6,4,5,7
   # FPR 6 now contains 0xC070 D800 0000 0935.
   # FPSCR now contains 0x8202 8000.
   # CR now contains 0x0800 0000.