Semiconductor packaging technology

Advanced flip chip assembly and testing, located at IBM Bromont—the largest OSAT in North America

Close-up of a semiconductor CPO fiber

IBM semiconductors chiplets and advanced packaging

IBM develops chiplet and advanced packaging technology capabilities to supercharge innovations for AI and logic.

By bringing multiple technologies together at the package level to increase performance and reduce cost, our frameworks enable a new paradigm for semiconductor innovations. It is a new pathway to meet AI’s increasing performance demands.

IBM’s Bromont, Canada facility transforms the world’s most advanced semiconductors into state-of-the-art microelectronic components. These elements are used in the entire line of IBM systems as well as in a wide range of products produced by its OEM customers.

With over 50 years of package assembly and test experience, Bromont is the largest outsourced semiconductor assembly and test (OSAT) facility in North America. It is also one of the largest exporters in Canada, manufacturing over 100,000 advanced flip chip modules each week.

Powering the future of AI infrastructure through advanced packaging

From chiplet integration and co-packaged optics to wafer-scale systems, IBM is delivering the advanced packaging technologies that enable the next generation of AI, high-performance computing, networking, aerospace and mission-critical systems. 

Advanced packaging has become the foundation for modern computing. As AI models grow larger and system performance demands increase, success depends on more than silicon alone. IBM combines decades of packaging innovation, manufacturing expertise and advanced assembly technologies to deliver scalable solutions that push the boundaries of performance, bandwidth, power efficiency and reliability.

Close-up of a microelectronic testing setup with precision probes and an optical inspection device over a chip

IBM Bromont: More than 50 years of advanced packaging leadership

Located in Québec, Canada, IBM Bromont is one of North America's premier semiconductor packaging and test facilities. Since 1972, Bromont has developed and manufactured advanced packaging solutions for enterprise computing, AI, networking, aerospace, defense, healthcare and other demanding industries.

With over 850,000 square feet of manufacturing space, Bromont combines advanced assembly, test, characterization, package design and optoelectronic integration capabilities within a highly automated production environment. The site serves both IBM products and a growing ecosystem of external technology partners.

Bromont is uniquely positioned to bridge innovation and production, with development activities supported through its partnership with C2MI and IBM's broader research ecosystem.

Aerial view of testing bromont building

Packaging the future of AI

No single packaging architecture can satisfy all AI infrastructure requirements. Future systems will rely on a combination of chiplet integration, optical interconnects, wafer-scale architectures and advanced manufacturing technologies. IBM's portfolio spans these critical domains, providing customers with scalable solutions from research through high-volume production.

Rows of illuminated server racks in a high-performance data center

MFIT™ Technology: Enabling the chiplet era

As AI and high-performance computing systems become increasingly complex, chiplet architectures require new approaches for connecting processors, memory and accelerators. IBM's MFIT™ technology provides a highly scalable platform for integrating multiple chips within a compact package while enabling exceptional performance and manufacturability.

Built around advanced organic redistribution layer interposers and embedded bridge technologies, MFIT™ supports high-density interconnects, improved signal integrity and efficient system scaling. The approach enables customers to achieve the benefits of advanced multichip integration while maintaining a practical path to high-volume manufacturing.

Designed for next-generation AI and HPC platforms, MFIT™ provides the flexibility required to bring together diverse silicon technologies into a single high-performance package.

Technician servicing semiconductor manufacturing equipment while kneeling beside an open control panel

Co-packaged optics: Rethinking data movement

AI infrastructure is driving unprecedented bandwidth requirements. Moving data efficiently is becoming as important as processing it. IBM's co-packaged optics (CPO) solutions bring optical connectivity closer to compute, reducing latency, increasing bandwidth and improving overall system efficiency.

IBM combines years of optoelectronic packaging expertise with advanced assembly technologies to support high-density optical integration for next-generation AI and hyperscale data centers. These solutions are designed to enable both scale-up and scale-out architectures while addressing the growing power challenges of traditional electrical interconnects.

Through its lab-to-fab ecosystem, IBM supports customers from development through production, helping accelerate deployment of future optical infrastructure.

Close-up of a microchip testing station with optical inspection lenses and precision positioning equipment

Wafer scale integration: Expanding the limits of compute

IBM's wafer-scale integration (WSI) platform represents a fundamentally different approach to system design. Rather than assembling multiple packaged devices together, WSI enables entire wafers to operate as highly integrated computing systems.

The result is unprecedented bandwidth, exceptional power efficiency and the ability to support massive AI and high-performance computing workloads. IBM's architecture combines advanced interconnects, vertical power delivery, integrated memory solutions and innovative cooling technologies into a single wafer-scale platform.

With years of development experience and demonstrated operational systems, IBM continues to advance WSI as a key technology for future AI infrastructure.

Close-up of a colorful semiconductor wafer with repeating microchip patterns in a grid layout

High-volume packaging built for today's most demanding systems

While IBM continues to pioneer future packaging technologies, it remains a leader in proven high-volume manufacturing platforms such as flip-chip BGA (fcBGA) and system-in-package (SiP). These technologies support a broad range of applications requiring high performance, reliability, thermal capability and complex multichip integration.

IBM's advanced fcBGA and SiP solutions are deployed across enterprise computing, networking, communications and specialized applications. The company's experience with large body sizes, dense interconnects and high-power designs enables customers to bring sophisticated products to market with confidence.

Backed by decades of manufacturing expertise, IBM continues to evolve these established packaging platforms to meet modern system requirements.

Close-up of a semiconductor package with exposed chip dies and fine wire connections on a test fixture
Capabilities

fcBGA and SiP focus 

  • Package size from 15 mm to 93 mm (proof of concept up to 105 mm) 
  • Die size from 2 x 2 mm to 27 x 32 mm 
  • Design packaging to support: >400A
  • Thermal solutions supporting: >400W
  • SiP, AoP SiP and Hybrid SiP
    • Close die and components positioning
    • Higher bandwidth and lower power
    • Better signal integrity
    • Smaller system level footprint
  • >400 components per module 
  • >23 different PNs per module 
  • Dual-sided components
Close-up cross-sectional view of layered electronic components with solder joints and metallic interconnects

  • Digital, analog, mixed signal, RF
  • Module, wafer and system level test development and characterization
  • Multisite programming
  • Test time reduction
  • Test program migration
  • Test pattern conversion (STIL, WGL)
  • Probe card, load board, system level test (SLT) board design, fab and validation
  • On load board test solutions
Close-up of a microchip secured in a test socket on a circuit board with visible contact pins

Design

  • System level integration mentality
  • Design team ITAR compliant under CGP of Canada 
  • Most advanced set of design tools
  • Customized automation and checking

Characterization

  • Industry-leading analytical techniques through the entire technology stack
  • Physical failure analysis
  • Materials composition 
  • Process characterization 

Modeling

  • Broad experience-based package reliability insight
  • Mathematically-proprietary algorithms, code, properties and models 
  • Predicted confidence bounds statistically linked to manufacturing data
Close-up of a semiconductor wafer with repeating chip patterns and metallic circuit structures

CPO—CSPO turnkey solution

  • EIC + PIC Assembly
  • Optical Fiber Array Attach 
  • CSOP Test 
  • CPO/SiP Assembly 
  • CPO/SiP Test

CPO development highlights

  • Increase of fiber density
  • 125μm pitch with 80μm fiber diameter
  • Assembly of ribbon with 35 fibers
  • Laser attach
  • On-die laser
  • Integrated connectors
Close-up of a precision dispensing machine applying material to electronic components on a circuit board

Why IBM assembly and test services?

50+ years of technology development and manufacturing

1972: Bromont site inauguration
1996: Worldwide supplier for gaming console processors
2016: z13 system—8 core chip 5,2Ghz on organic
2018: SiP, small cards—Z® program—encryption hardware
2022: 50-year anniversary

Specific environment to serve aerospace and defense

  • ITAR
  • Controlled unclassified information (CUI)
  • SECRET

IBM Ecosystem: From development to HVM

Full process flow capability from materials synthesis at MRL all the way through to assembly and test. Focused on enabling 3DHI technology with hybrid bonding, HD substrate enablement and DBHi bridge technology. IBM Bromont and OEM use 50 years of manufacturing experience serving both IBM and external customers for advanced flip ship, SiP and test production.

Quebec's clean energy advantage

  • The province relies heavily on hydroelectric power, a clean and renewable energy source.
  • 99% of all energy produced in Quebec is renewable.
  • Greenhouse gas (GHG) emissions from Quebec’s hydroelectric generating stations are 70 times less than coal-fired power stations.

  • Quebec has one of the lowest carbon-intensive electricity grids in the world.
  • Quebec’s power grid, the largest in North America, is one of the most reliable systems in the world.
  • Since 2013, Quebec has had a Greenhouse Gas Emission Cam-and-Trade System (SPEDE) in place to combat climate change.

  • Quebec has access to ample freshwater resources, essential for the semiconductor industry.

  • The government of Quebec committed to reducing greenhouse gas (GHG) emissions by 37.5% from 1990 levels by 2030.
  • Quebec has also committed to becoming carbon neutral by 2050.

Development labs

IBM's development labs located in the Northeast Corridor drive semiconductor technology innovation for the future of computing.

The IBM Watson Research Center in Yorktown Heights, New York.
Yorktown Heights, New York
The largest industrial research organization in the world, home to over 1,500 scientists, engineers and designing what's next in computing.
Scientist in the IBM Albany Lab
Albany, New York
100,000 square feet of semiconductor fab space, with many of the industry's biggest breakthroughs coming from this site. 
Manufacturing floor with assembly workstations, equipment racks, and a person using a computer along a marked aisle
Bromont, Quebec, Canada
IBM Bromont leverages its partnership with C2MI to take advantage of state-of-the-art equipment from over 70 equipment manufacturers.

Bromont news

Demand for chips continues to surge from AI and cloud computing advances. The Canadian and Quebec governments are partnering with IBM to solidify the future of the chip supply chain in North America by advancing the assembly, testing and packaging capabilities at IBM's plant in Bromont, Quebec.

Among the three entities, they will invest up to CAD 187 million in advancing the assembly, testing and packaging capabilities at the plant, enabling IBM to further its research and development of methods for scalable manufacturing and other advanced assembly processes.

Business people talking in office environment

Bromont is embarking on a journey of digital transformation, set to launch in May 2024, to elevate their semiconductor packaging and testing processes to the forefront of smart manufacturing.

This initiative will build a robust data fabric foundation, facilitating the integration of advanced AI/ML technologies. The smart factory will enable predictive and real-time monitoring for quality inspections and utilize big data analytics to proactively predict equipment failures. A control tower will also be implemented to centralize critical data and insights, enabling informed decision-making across management levels.

With these enhancements in asset performance and quality management, Bromont aims to improve operational efficiency and reliability, setting a new standard in the industry.

Two robot devices on a assembly line

Phase 1 aims to increase the assembly and test capacity of advanced fcBGA packaging technologies, while also adding capacity for Si Photonics technologies assembly. Phase 1.5 of the expansion plan will add wafer bumping and fan-out wafer-level packaging capabilities by 2H 2026.

This addition will create a complete North American solution for both R&D and high-volume manufacturing that leverages collaboration with IBM's research centers for lab-to-fab synergies.

Furthermore, IBM is working with development partner C2MI, located beside IBM Bromont, to finalize plans to add wafer finishing operations for 2.5D Si Interposer and 3D solutions. Production for this addition to the C2MI site is also scheduled for 2H 2026.

Aerial view of testing bromont building

Research

Close-up of micro device on machinery
Chiplet and packaging
Enabling multi die chiplet architectures for next generation AI accelerators by developing differentiated interconnect technologies in an open ecosystem.
IBM researcher holding 300mm IBMQuantum Nighthawk wafer
What is chip packaging?
If you’ve ever read anything about semiconductors, you’ve probably seen a photo of someone holding up a wafer. They’re silicon disks containing hundreds of future computer chips.
Close-up of a Analog AI Silicon wafer used in semiconductor manufacturing
Semiconductor fabrication and packaging
We’re developing new materials for both the smallest length scale (<20 nm) and largest length scale (>20 mm) of semiconductor fabrication.
Close-up cross-sectional view of layered electronic components with solder joints and metallic interconnects
IBM Research unveils hybrid bonding for packaging chips
Researchers at IBM and ASMPT have hit a milestone with a hybrid bonding technology that drastically reduces the I/O interconnection size of bonding needed between two chiplets, paving the way for a myriad of new computer chip designs.
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