Header/self-defining section, based on the address of SMF record type 113 + the offset value in SMF113DOF

This section contains the common SMF subtype header fields and the triplet fields (offset/length/number), if applicable, that locate the other sections on the record.

Offsets Name Length Format Description
0 0 SMF113_2_CTS 8 binary Time when the hardware data collection run started in STCK format
8 8 SMF113_2_CTM 8 binary Time when this SMF record was written in STCK format.
16 10 SMF113_2_CPU# 1 binary Start of changeThis field is deprecated, use SMF113_2_CpuId instead. Processor number for which the hardware counters in SMF113_2_CR are recorded. Note that zero is a valid processor number.End of change
17 11 SMF113_2_CpuProcClass 1 binary The processor type for which the hardware event counters are recorded. Is one of the following:
0
Standard CP
2
zAAP
4
zIIP
18 12 SMF113_2_CF 2 binary Record flags:
Bit
Meaning when set
0
First SMF record for the hardware data collection run. The counter values are the initial values at the beginning of the run.
1
Intermediate SMF record, written by the system at defined intervals during the hardware data collection run. The counter values are intermediate values. The interval is based on the SMFINTVAL parameter specified at the start of the hardware data collection run.
2
Final SMF record written for this hardware data collection run. The counter values are the final values.
3
Indicates that the SMF record was written on non-standard hardware.
4
When ON, the hardware indicated the hardware has lost counter data during the current interval.
4-15
Reserved.
20 14 SMF113_2_CTRVN1 2 binary First counter version number. This number is increased when there is a change to the meaning of a counter or a change to the number of the installed counters in the basic or problem-state counter sets.
Start of change22End of change 16 SMF113_2_CTRVN2 2 binary Second counter version number. This number is increased when there is a change to the meaning of a counter or a change to the number of the installed counters in the crypto-activity or extended counter sets.
Self-defining section
24 18 SMF113_2_CSOF 4 binary Offset to counter set section, from beginning of SMF record type 113
28 1C SMF113_2_CSLN 2 binary Length of counter set sections
30 1E SMF113_2_CSON 2 binary Number of counter set sections
32 20 SMF113_2_CDOF 4 binary Offset to counters section, from beginning of SMF record type 113
36 24 SMF113_2_CDLN 2 binary Length of counters sections
38 26 SMF113_2_CDON 2 binary Number of counter sections
CPU information section
40 28 SMF113_2_CPSP 4 binary Processor speed for which the hardware event counters are recorded. Speed is in cycles/microsecond.
44 2C SMF113_2_MachType 4 EBCDIC The machine type.
48 30 SMF113_2_MachModel 16 EBCDIC The machine model.
Start of change64End of change Start of change40End of change Start of changeSMF113_2_CpuIdEnd of change Start of change2End of change Start of changebinaryEnd of change Start of changeProcessor ID for which the hardware event counters are recorded.

Note that zero is a valid processor number.

End of change
Start of change66End of change Start of change42End of change Start of change*End of change Start of change2End of change Start of changebinaryEnd of change Start of changeReservedEnd of change
Start of change68End of change Start of change44End of change Start of changeSMF113_2_SeqCodeEnd of change Start of change16End of change Start of changeEBCDICEnd of change Start of changeThe machine sequence code.End of change
Note: For more information on machine type and machine model, see Resource Link home page.
Parent topic: Subtype 2