FTXBK | Back to Index page

| Prolog Control Block Contents FTXBK DSECT Storage Layout Cross Reference (Contains links to field and bit definitions) |
Programming Interface Information: This information is NOT intended to be used as Programming Interfaces of z/VM.

FTXBK Prolog | Top of page

     NAME       : HCPFTXBK
     DESCRIPTION: Frame Table Extent Block
     DSECT      : FTXBK
     FUNCTION   : Contain Frame Table scan range addresses
     CREATED BY : HCPIFTIX
     DELETED BY : NA
     LOCATED BY : RSAFTXFL - FTXBK chain for frames < 2G
                  RSAFTXFG - FTXBK chain for frames >= 2G
                  RSAFTXGC - Global FTXBK chain (contains all FTXBKs in
                  no guaranteed order)
     RELOCATION CONSIDERATIONS : None
     NOTES      :
                  The RSMBK contains 2 FTXBks, one for <2G and one for
                  >2G.  In a system with nothing >2G, there will still be
                  these 2 FTXBKs.  In order to indicate that an FTXBK is
                  not actually describing anything, a bogus value will be
                  used for the FRMTE ranges.  Any bogus value would do.
                  FTXSTART = zero is the chosen bogus value.
     SERIALIZED :
                  Changes to the FTXBK fwd/bwd pointers are serialized
                  by virtue of a single processor running in HCPSYNSV
                  and all the other processors spinning in HCPSYNWT.
                  FTXBK lo/hi values are serialized by virtue of being
                  updated before the FTXBK is added to the chain of
                  FTXBKs, and never changed thereafter.
                  FTXBK start/end values are not serialized.  They are
                  initialized to the FTXBK hi/lo values respectively,
                  before the FTXBK is added to the chain of FTXBKs.
                  Subsequent updates will only lower FTXStart or raise
                  FTXEnd.  The start/end pair will always describe a
                  valid range.
                  Storage is accessed in block-concurrent blocks of 8
                  bytes each.  That means a STMG or LMG operates on each
                  8-byte block one at a time.
                  Consider simultaneous tasks: 1 updating, 1 reading.
                  If Updater completes the STMG updating of the FTXBK
                  before Reader reads the new values, then Reader will
                  LMG a valid start-end pair.
                  Since FTXSTART/FTXEND are not serialized, we need to
                  consider incomplete updates.  If Updater does not
                  complete the STMG updating of the FTXBK before Reader
                  reads the new values, then Reader will LMG a start-end
                  pair that may not be accurate.  The issue is:  will
                  that pair be dangerous?
                  Let's consider four scenarios.
                  - scenario 1, storage initialization has not made any
                  frames available yet.
                  - scenario 2, the last frame in the lo/hi range is the
                  first to be made available.
                  - scenario 3, some frame in the midst of the lo/hi
                  range is the first to be made available.
                  - scenario 4, some lower frame in the lo/hi range is
                  the next to be made available.
                  Scenario 1, the Reader executes LMG and sees that the
                  starting address is higher that the ending address.
                  This tells the frame table scanner that processing of
                  this FTXBK has been completed.
                  updater          start/end         reader
                  10   1          LMG 10/1
                  Scenario 2, frame 10 is the first to be made available.
                  Updater's STMG and Reader's LMG execute simultaneously.
                  The timing of the processors is such that the LMG reads
                  storage before the STMG completes.  The result for
                  Reader is the same as scenario 1.
                  updater          start/end         reader
                  10   1
                  STMG 10/10         10   1          LMG 10/1
                  Scenario 3, frame 5 is the first to be made available.
                  Updater's STMG and Reader's LMG execute simultaneously.
                  The timing of the processors is such that the LMG reads
                  storage before the STMG completes.  The result for
                  Reader is the same as scenario 1.
                  updater          start/end         reader
                  10   1
                  STMG 5/5           5    1          LMG 5/1
                  Scenario 4, frame 4 is the next to be made available.
                  Updater's STMG and Reader's LMG execute simultaneously.
                  The timing of the processors is such that the LMG reads
                  storage before the STMG completes.  The result for
                  Reader is a valid range 4-5.
                  updater          start/end         reader
                  5    5
                  STMG 4/5           4    5          LMG 4/5

FTXBK Control Block Content | Top of page

     FTXBK DSECT
    Top of page

    Hex   Dec Type/Val   Lng Label (dup)    Comments
    ---- ---- --------- ---- -------------- --------
    0000    0 Structure      FTXBK          Frame Table Extent Block
    0000    0 Address      4 FTXNEXT        Next FTXBK address
    0004    4 Address      4 FTXPREV        Previous FTXBK address
    0008    8 Address      4 FTXNEXTG       Global next; chain is unordered;
                                            includes <2G and >2G
                                            FTXBKs; chain ends with pointer
                                            of zero
    000C   12 Address      4 *              Reserved for IBM use
    0010   16 Address      8 FTXlo          Host logical address of FRMTE at
                                            which this range of real storage
                                            begins.
    0018   24 Address      8 FTXhi          Host logical address of FRMTE at
                                            which this range of real storage
                                            ends.
    0020   32 Address      8 FTXSTART       Host logical address of FRMTE at
                                            which to start frame table scan
                                            for this extent. FTXSTART will be
                                            within the range FTXlo-FTXhi.
    0028   40 Address      8 FTXEND         Host logical address of FRMTE at
                                            which to end frame table scan for
                                            this extent. FTXEND will be
                                            within the range FTXlo-FTXhi.
    0030   48 Dbl-Word     8 *              Reserved for IBM use
    0038   56 Dbl-Word     8 *              Reserved for IBM use
              00000008       FTXSIZE        (*-FTXBK+7)/8 FTXBK size in
                                            doublewords

FTXBK Storage Layout | Top of page

    *** FTXBK - Frame Table Extent Block
    *
    *     +---------------------------+---------------------------+
    *   0 |         FTXNEXT           |         FTXPREV           |
    *     +---------------------------+---------------------------+
    *   8 |         FTXNEXTG          |///////////////////////////|
    *     +---------------------------+---------------------------+
    *  10 |                        FTXLO                          |
    *     +-------------------------------------------------------+
    *  18 |                        FTXHI                          |
    *     +-------------------------------------------------------+
    *  20 |                       FTXSTART                        |
    *     +-------------------------------------------------------+
    *  28 |                        FTXEND                         |
    *     +-------------------------------------------------------+
    *  30 |///////////////////////////////////////////////////////|
    *     +-------------------------------------------------------+
    *  38 |///////////////////////////////////////////////////////|
    *     +-------------------------------------------------------+
    *  40
    *
    *** FTXBK - Frame Table Extent Block

FTXBK Cross Reference | Top of page

    Symbol         Dspl Value
    -------------- ---- -----
    FTXhi          0018
    FTXlo          0010
    FTXEND         0028
    FTXNEXT        0000
    FTXNEXTG       0008
    FTXPREV        0004
    FTXSIZE        0038 00000008
    FTXSTART       0020

This information is based on z/VM 7.2.0 Last updated on 24 Jun 2020 at 09:28:21 EDT.
Copyright IBM Corporation, 1990, 2020