PAG64 | Back to Index page

| Prolog Control Block Contents PAG64 DSECT Storage Layout Cross Reference (Contains links to field and bit definitions) |
Programming Interface Information: This information is NOT intended to be used as Programming Interfaces of z/VM.

PAG64 Control Block Content | Top of page

     PAG64 DSECT
    Top of page

    Hex   Dec Type/Val   Lng Label (dup)    Comments
    ---- ---- --------- ---- -------------- --------
    0000    0 Structure      PAG64          Page Table Entry
    0000    0 Dbl-Word     8 PAGGENTR       PTEs are 8 bytes
          PAGGPTOM = X'FFFFFFFFFFFFF800' represents the mask that
              could be used to isolate Page Table Origin (PTO)
              given the address of a PTE.
          64-bit mask  X'FFFFFFFFFFFFF800'
              00FFFFFF       PAGGPTMH       X'FFFFFFFF' Isolate high half of
                                            PTOM
              00FFF800       PAGGPTML       X'FFFFF800' Isolate low half of
                                            PTOM
          PAGGPFRA = X'FFFFFFFFFFFFF000' represents the mask that
              could be used to isolate the Page Frame Real Address
              from the address of a known PTE.  NOTE that an instance
              of this constant exists at PFXGPFRA.
          64-bit mask  X'FFFFFFFFFFFFF000'
              00FFFFFF       PAGGPFAH       X'FFFFFFFF' Isolate high half of
                                            PFRA
              00FFF000       PAGGPFAL       X'FFFFF000' Isolate low half of
                                            PFRA
          64-bit mask  X'0000000000000400'
          32-bit high  X'00000000'           High half of mask
              00000400       PAGGINVR       X'00000400' Isolate I bit
          64-bit mask  X'0000000000000200'
          32-bit high  X'00000000'           High half of mask
              00000200       PAGGPROR       X'00000200' Isolate P bit
          64-bit mask  X'0000000000000100'
          32-bit high  X'00000000'           High half of mask
              00000100       PAGGIEPR       X'00000100' Isolate IEP bit
          64-bit mask  X'0000000000000001'
          32-bit high  X'00000000'           High half of mask
              .... ...1      PAGGLOKR       X'00000001' Isolate L bit
          64-bit mask  X'00000000000000FE'
          32-bit high  X'00000000'           High half of mask
              1111 111.      PAGGRSDR       X'000000FE' Reserved for IBM use
          64-bit mask  X'0000000000000900'
          32-bit high  X'00000000'           High half of mask
              00000900       PAGGRSVR       X'00000900' Reserved bits, must
                                            be 0 in any valid z/Arch PTE when
                                            EDAT-1 does not apply and IEP is
                                            not installed
              00000800       PAGGRSVE       X'00000800' Reserved bits, must
                                            be 0 when EDAT-1 enabled or IEP
                                            is installed The following
                                            equates may only be used when the
                                            page is not resident (the PTE I
                                            bit is set and page is not IBR):
          64-bit mask  X'0000000000000500'
          32-bit high  X'00000000'           High half of mask
              00000500       PAGGXIVR       X'00000500' Isolate I bit *AND*
                                            'valid in XSTORE' bits. This is a
                                            non-architected software
                                            definition.
          64-bit mask  X'FFFFFFFF00000000'
              00FFFFFF       PAGGXBNH       X'FFFFFFFF' Isolate XSBN
              .... ....      PAGGXBNL       X'00000000' Low half of mask This
                                            is a non-architected software
                                            definition.
              00000000       PAGGXBNBL      0 Number of bits to the left of
                                            the XSBN. Can be used for
                                            shifting.
              00000020       PAGGXBNBR      32 Number of bits to the right of
                                            the XSBN. Can be used for
                                            shifting.
          64-bit mask  X'00000000FFFFC000'
              .... ....      PAGGXTSH       X'00000000' Isolate XS Timestamp
              00FFC000       PAGGXTSL       X'FFFFC000' Low half of mask This
                                            is a non-architected software
                                            definition.
              00000020       PAGGXTSBL      32 Number of bits to the left of
                                            the xstore time stamp. Can be
                                            used for shifting.
              0000000C       PAGGXTSBR      12 Number of bits to the right of
                                            the xstore time stamp. Can be
                                            used for shifting.
          64-bit mask  X'0000000000000004'
          32-bit high  X'00000000'           High half of mask
              .... .1..      PAGGXSRR       X'00000004' Isolate Xstore R bit
                                            (Reference bit) This is a
                                            non-architected software
                                            definition.
          64-bit mask  X'0000000000000001'
          32-bit high  X'00000000'           High half of mask
              .... ...1      PAGGXSLR       X'00000001' Isolate L bit (Lock
                                            bit). This is architected for
                                            LKPG when PTE is valid. It is
                                            used by software when PTE is
                                            invalid.
    0000    0 Signed       4 PAG64W0 (0)    PTE Word 0
    0000    0 Signed       4 PAGGPFRL       Bits 0-32 of 64 bit PFRA
    0004    4 Signed       4 PAGGPFRR       Bits 32-51 of 64 bit PFRA, plus
                                            12 status bits
              00000008       PAGGLENG       *-PAGGENTR Length of one page
                                            table entry
    0008    8 Signed       4 PAGGNEXT (0)   Next page table entry
    0000    0 Signed       4 *              Architected as bits 0-31 of the
                                            4K aligned page frame real
                                            address (if page is resident). If
                                            page isn't resident, this is used
                                            by software to store an XSTORE
                                            block number.
    0004    4 Signed       2 *              Architected as bits 32-47 of the
                                            4K aligned page frame real
                                            address (if page is resident). If
                                            page isn't resident & page is in
                                            xstore, this contains the first
                                            16 bits of the 20-bit xstore time
                                            stamp.
    0006    6 Bitstring    1 PAGGSTAT       Architected as bits 48-51 of the
                                            4K aligned page frame real
                                            address (if page is resident)
                                            followed by four flag bits.
              .... 1..1      PAGGSMBZ       X'09' PAGGSMBZ Must be zero in
                                            any valid PTE
              .... .1..      PAGGINVA       X'04' PAGGINVA PTE is invalid:
                                            I-bit. To turn off this bit,
                                            SHORT pg. serialization must be
                                            held unless the bit is being
                                            turned off by HPMA or by fastpath
                                            resolve which require only
                                            PCLONLY
              .... ..1.      PAGGPROT       X'02' PAGGPROT Page protected
                                            (read only): P-bit
              .... .1.1      PAGGSXVA       X'05' PAGGSXVA Page is invalid,
                                            but is valid in xstore This is a
                                            non-architected software
                                            definition.
    0007    7 Bitstring    1 PAGGSTA2       Contains non-architected software
                                            definitions when I-bit is on.
                                            Contains L-bit when I-bit if off.
              1111 111.      PAGGS2PG       X'FE' PAGGS2PG Reserved bits if
                                            PTE is valid Architected
                                            definitions when I-bit is off.
              .... ...1      PAGGS2LK       X'01' PAGGS2LK Lock bit (used by
                                            LKPG) when PTE is valid. Software
                                            definitions when I-bit is on.
              .... .1..      PAGGS2XR       X'04' PAGGS2XR R (Reference) bit
                                            if PTE is invalid, but valid in
                                            xstore
              .... ...1      PAGGS2XL       X'01' PAGGS2XL L (Lock) bit if
                                            PTE is invalid, but valid in
                                            xstore
    0000    0 Signed       4 PAGGXSBN       Xstore block number. Only valid
                                            when PTE is invalid and PGSXSTOR
                                            is set in corresponding PGSTE.
                                            For MDC PTEs, only valid when PTE
                                            is invalid in real storage, but
                                            valid in xstore. This is a
                                            non-architected software
                                            definition.
    0004    4 Signed       4 *              Bits 32-51 are the xstore time
                                            stamp. Only true when PTE is
                                            invalid and PGSXSTOR is set in
                                            corresponding PGSTE.
    0000    0 Dbl-Word     8 PAGGPASA2      PTRM 2nd ASA. For PTRM PTEs only,
                                            and only when PGMBK is on DASD or
                                            as a transient condition when the
                                            PGMBK is headed to/from DASD.
                                            Note that I and P bits must be
                                            preserved.

PAG64 Storage Layout | Top of page

    *** PAG64 - Page Table Entry
    *
    *     +-------------------------------------------------------+
    *   0 |                       PAGGENTR                        |
    *     +-------------------------------------------------------+
    *   8
    *
    *** PAG64 - Page Table Entry

    *** Overlay for PAGGENTR in PAG64
    *
    *     +---------------------------+---------------------------+
    *   0 |         PAGGPFRL          |         PAGGPFRR          |
    *     +---------------------------+---------------------------+
    *
    *** Overlay for PAGGENTR in PAG64

    *** Overlay for PAGGENTR in PAG64
    *
    *     +---------------------------+-------------+------+------+
    *   0 |///////////////////////////|/////////////|:GSTAT|:GSTA2|
    *     +---------------------------+-------------+------+------+
    *   8
    *
    *** Overlay for PAGGENTR in PAG64

    *** Overlay for PAGGENTR in PAG64
    *
    *     +---------------------------+---------------------------+
    *   0 |         PAGGXSBN          |///////////////////////////|
    *     +---------------------------+---------------------------+
    *   8
    *
    *** Overlay for PAGGENTR in PAG64

    *** Overlay for PAGGENTR in PAG64
    *
    *     +-------------------------------------------------------+
    *   0 |                      PAGGPASA2                        |
    *     +-------------------------------------------------------+
    *   8
    *
    *** Overlay for PAGGENTR in PAG64

PAG64 Cross Reference | Top of page

    Symbol         Dspl Value
    -------------- ---- -----
    PAGGENTR       0000
    PAGGIEPR       0000 00000100
    PAGGINVA       0006 04
    PAGGINVR       0000 00000400
    PAGGLENG       0004 00000008
    PAGGLOKR       0000 01
    PAGGNEXT       0008
    PAGGPASA2      0000
    PAGGPFAH       0000 00FFFFFF
    PAGGPFAL       0000 00FFF000
    PAGGPFRL       0000
    PAGGPFRR       0004
    PAGGPROR       0000 00000200
    PAGGPROT       0006 02
    PAGGPTMH       0000 00FFFFFF
    PAGGPTML       0000 00FFF800
    PAGGRSDR       0000 FE
    PAGGRSVE       0000 00000800
    PAGGRSVR       0000 00000900
    PAGGSMBZ       0006 09
    PAGGSTAT       0006
    PAGGSTA2       0007
    PAGGSXVA       0006 05
    PAGGS2LK       0007 01
    PAGGS2PG       0007 FE
    PAGGS2XL       0007 01
    PAGGS2XR       0007 04
    PAGGXBNBL      0000 00000000
    PAGGXBNBR      0000 00000020
    PAGGXBNH       0000 00FFFFFF
    PAGGXBNL       0000 00
    PAGGXIVR       0000 00000500
    PAGGXSBN       0000
    PAGGXSLR       0000 01
    PAGGXSRR       0000 04
    PAGGXTSBL      0000 00000020
    PAGGXTSBR      0000 0000000C
    PAGGXTSH       0000 00
    PAGGXTSL       0000 00FFC000
    PAG64W0        0000

This information is based on z/VM 7.2.0 Last updated on 24 Jun 2020 at 09:31:40 EDT.
Copyright IBM Corporation, 1990, 2020