Programming Interface Information: The Monitor Records are intended Programming Interfaces that allow the customer to write programs to obtain services of z/VM.

#### MRMTRCCC

Prolog
Control Block Contents
Cross Reference

#### MRMTRCCC Prolog

####

####

     DSECT NAME - MTRCCC
     FUNCTION - Map a Monitor record.
     LOCATED By -
            Through the Monitor Control Area
     REFERENCED CONTROL BLOCKS -
            MRRECHDR    Monitor Record Header
     NAME - MRMTRCCC
     DESCRIPTIVE NAME - Monitor Event Record
                        Domain 1 - Monitor Domain
                        Record 18 - CPU Capability Change
     DESCRIPTION - Record of a CPU Capability Change reported by the
                   Support Element.
     NOTES:
         1. For additional information about the format and
            meaning of the MTRCCC_STSI111 field, refer to the
            following book:
              - Principles of Operation for the layout of the
                STSI 1.1.1 output (first 180 bytes) which is
                documented in Chapter 10 under "STORE SYSTEM
                INFORMATION". The field meanings are there also.

    MRMTRCCC Control Block Contents

    Offsets
    Dec Hex  Type       Len  Name (Dim)             Description

      0   0  Structure  216  MTRCCC                 Start of monitor record
      0   0  Character    0  MTRCCC_MRHDR           Record header - see MRRECHDR
                                                    for details
      0   0  Character   20  MRHDR
      0   0  Unsigned     2  MRHDRLEN               record length in bytes
      2   2  Unsigned     2  MRHDRZER               field of zeros
      4   4  Unsigned     1  MRHDRDM                domain identifier
      5   5  Unsigned     1  *
      6   6  Unsigned     2  MRHDRRC                record identifier
      8   8  Character    8  MRHDRTOD               Time at which this record was
                                                    built. In time-of-day (TOD)
                                                    clock format. See IBM System
                                                    370 XA Principle of Operation
                                                    for explanation of format.
     16  10  Character    4  *
     20  14  Character    0  MRHDR_END              End of header
     20  14  Unsigned     4  MTRCCC_CPUCAPAB        The capability of a CPU in
                                                    the configuration
     24  18  Unsigned     4  MTRCCC_SCPCAPAB        The capability of a secondary
                                                    CPU in the configuration
     28  1C  Unsigned     4  MTRCCC_NCPCAPAB        The nominal capability of a
                                                    CPU in the configuration
     32  20  Unsigned     1  MTRCCC_SYSCCR          Capacity-Change Reason.
     33  21  Unsigned     1  MTRCCC_SYSCAI          Capacity-Adjustment
                                                    Indication.
     34  22  Bitstring    1  MTRCCC_SSI1FLGS        Miscellaneous flags.
              1... ....      MTRCCC_SSI1TRNS        Transient CCR and CAI.
              .1.. ....      *
              ..1. ....      *
              ...1 ....      *
              .... 1...      *
              .... .1..      *
              .... ..1.      *
              .... ...1      *
     35  23  Unsigned     1  *                      Reserved and available for
                                                    IBM use.
     36  24  Character  180  MTRCCC_STSI111         First 180 bytes of the STSI
                                                    1.1.1 output.
    216  D8  Character    0  MTRCCC_END

    MRMTRCCC Cross Reference

                          Hex           Hex
    Name                 Offset Length Value

    MRHDR                      0     20
    MRHDR_END                 14      0
    MRHDRDM                    4      1
    MRHDRLEN                   0      2
    MRHDRRC                    6      2
    MRHDRTOD                   8      8
    MRHDRZER                   2      2
    MTRCCC                     0    216
    MTRCCC_CPUCAPAB           14      4
    MTRCCC_END                D8      0
    MTRCCC_MRHDR               0      0
    MTRCCC_NCPCAPAB           1C      4
    MTRCCC_SCPCAPAB           18      4
    MTRCCC_SSI1FLGS           22      1
    MTRCCC_SSI1TRNS           22           80
    MTRCCC_STSI111            24    180
    MTRCCC_SYSCAI             21      1
    MTRCCC_SYSCCR             20      1

    This information is
    based on z/VM V6R1.0.

    Last updated on 09 Aug 2011 at 14:32:13.

    Copyright IBM Corporation, 1990, 2011