Troubleshooting
Problem
In rare cases, after flashing Unified Extensible Firmware Interface (UEFI) and Field Programmable Gate Array (FPGA) on an EXA scaled 2-node server, and after performing a DC power cycle to activate, the system stays powered off and does not restart. TheLight Path Diagnostics (LPD) panel checkpoint display on both nodes alternates between "00" and "bb".
Resolving The Problem
Source
RETAIN tip: H203090
Symptom
In rare cases, after flashing Unified Extensible Firmware Interface (UEFI) and Field Programmable Gate Array (FPGA) on an EXA scaled 2-node server, and after performing a DC power cycle to activate, the system stays powered off and does not restart.
The Light Path Diagnostics (LPD) panel checkpoint display on both nodes alternates between "00" and "bb".
Affected configurations
The system may be any of the following IBM servers:
- System x3850 X5, type 7143, any model
- System x3850 X5, type 7145, any model
- System x3850 X5, type 7146, any model
- System x3850 X5, type 7191, any model
- System x3950 X5, type 7145, any model
The system is configured with one or more of the following IBM Options:
- IBM MAX5 V2 for System x, Option part number 88Y6529
- IBM MAX5 for System x, Option part number 59Y6265
This tip is not software specific.
Solution
This behavior is corrected in Integrated Management Module (IMM) v1.30 (Build ID: yuooc7e) and Field Programmable Gate Array (FPGA) v2.01 (Build ID: g0ud72b), which are currently available.
These files are available by selecting the appropriate Product name, Product machine type, and Operating system on IBM Support's Fix Central web page, at the following URL:
Workaround
User can recover the system by AC power cycling and flashing again if needed:
- Remove AC power from both nodes.
- Reconnect AC power to both nodes.
- Verify both nodes' firmware level is at the new version, otherwise, flash the firmware again.
Additional information
This issue is caused by a synchronization issue on EXA 2-node when performing FPGA firmware activation. IMM tries to activate new FPGA code when the system is not completely ready. The result is a power permission block, as indicated by the 00-bb on the checkpoint display.
Document Location
Worldwide
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Document Information
Modified date:
30 January 2019
UID
ibm1MIGR-5087851