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Identifying “Store Into Instruction Stream” (SIIS) Inefficiency by Using CPU MF Counters

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Abstract

Abstract: This document describes a new technique to identify Store Into Instruction Stream (SIIS) inefficiency by using CPU MF Counters. There are several components to the document. This paper describes what is SIIS, CPU MF Counters and the new metric, SIIS Indicator %, along with thresholds and recommended actions. Also provided are the slides that accompany the paper. In addition, there is also a link to a 2006 TechDocs that describes the processor design considerations and the code it expects to execute. Finally, there is a paper that contains remediation examples of programs with SIIS impacts.

Content

Identifying “Store Into Instruction Stream” (SIIS) Inefficiency by Using CPU MF Counters - Paper
Identifying “Store Into Instruction Stream” (SIIS) Inefficiency by Using CPU MF Counters - Slides
2006 TechDocs: IBM System z and eserver zSeries Processor Performance Design Considerations 
IBM zSystems: Remediation of Programs with SIIS Impacts

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Document Information

Modified date:
31 May 2022

UID

WP102806