A fix is available
APAR status
Closed as new function.
Error description
See APAR abstract
Local fix
Problem summary
**************************************************************** * USERS AFFECTED: High Level Assembler Programs using branch * * relative and register immediate instructions * * These new instructions are available on * * CMOS processors. * **************************************************************** * PROBLEM DESCRIPTION: MSGASMA057E when trying to use any of * * the new instructions introduced by the * * immediate and relative facility. * **************************************************************** * RECOMMENDATION: * **************************************************************** The new instructions added by the immediate and relative instruction facility, the compare and move extended facility and the checksum facility are not in the current opcode tables
Problem conclusion
Temporary fix
Comments
The instructions have been added to the universal and ESA opcode tables. Additional changes have also been made in ASMA28 and ASMA29 in support of the new immediate operands. Additional information. The complete list of mnemonics added by this APAR is AHI BRXH CLCLE MSR J JO JM JNP BRAS BRXLE LHI MS JE JH JNL JNO BRC CKSM MVCLE TMH JZ JL JNZ JNM BRCT CHI MHI TML JNE JNH JP NOTE: Check on applicability of this New Function. The new instructions are available on CMOS processors. The following documentation changes are also required. SC26-4941 and SC26-8264 HLASM Programmer's Guide Change the following message as indicated: ASMA031 Invalid immediate field Add the following text to the explanation. For RI and RSI format instructions, this indicates that the immediate value lies outside the acceptable range, nominally -32768 to 32767. Add the following messages: ASMA056 Absolute value found when relocatable value expected Explanation: An absolute expression has been used as the immediate field in a branch-relative instruction. The immediate field in a branch-relative instruction is used as signed number of halfwords relative to the current location counter. The use of an absolute expression for this value may cause unpredictable results. System action: The instruction assembles as written Programmer Response: Supply a relocatable expression. Severity: 4 ASMA058 Invalid target of branch relative instruction Explanation: One of the following has occurred: 1) The target expression is not in the same control section as the instruction. 2) The target expression is an odd value and therefore cannot be represented as a number of halfwords. System action: The instruction assembles as zero Programmer Response: Supply a valid target value that is on a halfword boundary and within the same control section. Severity: 8 SC26-4940 and SC26-8265 HLASM Language Reference Add the following text and table to the section titled 'Branching with Extended Mnemonic Codes' The branch relative on condition instruction, BRC, also has a set of extended mnemonics, similar to those used for BC and BCR. To avoid any possible confusion with the current mnemonics, the branch-relative extended mnemonics all start with the letter J, meaning Jump. Extended Code Meaning Format Machine instruction equivalent J label Unconditional Jump RI BRC B'1111',label JO label Jump if Overflow RI BRC B'0001',label JH label Jump if High RI BRC B'0010',label JP label Jump if Positive RI BRC B'0010',label JL label Jump if Low RI BRC B'0100',label JM label Jump if Minus RI BRC B'0100',label JE label Jump if Equal RI BRC B'1000',label JZ label Jump if Zero RI BRC B'1000',label JNO label Jump if Not Overflow RI BRC B'1110',label JNH label Jump if Not High RI BRC B'1101',label JNP label Jump if Not Positive RI BRC B'1101',label JNL label Jump if Not Low RI BRC B'1011',label JNM label Jump if Not Minus RI BRC B'1011',label JNE label Jump if Not Equal RI BRC B'0111',label JNZ label Jump if Not Zero RI BRC B'0111',label In the section titled 'Statement Formats' Add RI and RSI to the list of formats of length 4 In the section titled 'Addresses' Add a new section titled 'Relative Address' with the following text A relative address is specified by coding one expression. The expression may be relocatable or absolute. If a relocatable expression is used, then the assembler will convert the value to a 16-bit signed number of halfwords relative to the current location counter and then use that value in the object code. An absolute value may be used for a relative address, but the assembler will issue a warning message as it uses the value directly and this may cause unpredictable results. NOTE: Various statements throughout this manual that all addresses must be in base-displacement form are no longer valid with the addition of relative addresses to the IBM System/390 Change Figure 21 'Format of Addresses in Object Code' by adding the following two entries RI 8 4 4 16 +-------------+------+------+--------------------------+ | | |Opcode| | | Op Code | R1 | digit| I2 | | | | (0-F)| | +-------------+------+------+--------------------------+ RSI 8 4 4 16 +-------------+------+------+--------------------------+ | | | | | | Op Code | R1 | R3 | I2 | | | | | | +-------------+------+------+--------------------------+ In the section titled 'Examples of Coded Machine Instructions' Add two new sections, as follows: RI Format The operand fields of RI-format instructions designate a register and a 16-bit immediate operand, with the following exception: In BRC branching instructions, a 4-bit branching mask with a value between 0 and 15 inclusive, replaces the register designation. Symbols used to represent registers (See REG1 below) are assumed to be equated to absolute values between 0 and 15. The 16-bit immediate operand has two different interpretations, depending on whether the instruction is a branching instruction or not. For non-branching RI-format instructions, the immediate value is treated as a 16-bit signed binary integer (that is a value between -32768 and +32767). This value may be specified using self-defining terms or equated symbols. Examples ALPHA1 AHI REG1,2000 ALPHA2 MHI 3,1234 BETA1 TMH 7,X'8001' When assembled, the object code for the instruction labeled BETA1, in hexadecimal, is A7708001 where A7.0 is the operation code 7 is register R1 8001 is the immediate data I2 NOTE: All immediate-operand evaluations are performed using 32-bit arithmetic but only the low order 16 bits are placed into the object code. As some instructions treat the immediate field as a signed value, some results may be unexpected. For example, the following TMH with a hexadecimal mask assembles as expected and will execute as expected TMH 1,X'8001' object code is X'A7108001' If we change it to a AHI as follows AHI 1,X'8001' object code is X'A71A8001' this will assemble correctly, but execution will use a value of -32767 for the addition. This is due to the interpretation of the immediate field as a signed 16-bit value. A similar example is AHI 1,32769 object code is X'A71A8001' which will assemble into the object code as shown, the same as the previous example and again a value of -32767 will be used for the addition. NOTE: Later versions of HLASM recognize 2 types of immediate data operands for non-branching RI-format instructions depending on the type of instruction: 16-bit signed values - eg, AHI, LHI 16-bit logical mask values - eg, TMH, TML This means that instructions such as AHI 1,32769 and AHI 1,X'8001' will be rejected. To specify -32767 as a hexadecimal self-defining term, code: AHI 1,X'FFFF8001'. For branching RI-format instructions, the immediate value is treated as a 16-bit signed binary integer representing the number of halfwords to branch relative to the current location. The branch target may be specified as a label in which case the assembler will calculate the immediate value and perform some checking of the value. The branch target may also be specified as an absolute value in which case the assembler will issue a warning before it assembles the instruction. Examples ALPHA1 BRAS 1,BETA1 ALPHA2 BRC 3,ALPHA1 BETA1 BRCT 7,ALPHA1 When assembled, the object code for the instruction labeled BETA1, in hexadecimal, is A776FFFC where A7.6 is the operation code 7 is register R1 FFFC is the immediate data I2 a value of -4 decimal RSI Format The operand fields of RSI-format instructions designate two registers and a 16-bit immediate operand. Symbols used to represent registers (See REG1 below) are assumed to be equated to absolute values between 0 and 15. The immediate value is treated as a 16-bit signed binary integer representing the number of halfwords to branch relative to the current location. The branch target may be specified as a label in which case the assembler will calculate the immediate value and perform some checking of the value. The branch target may also be specified as an absolute value in which case the assembler will issue a warning before it assembles the instruction. Examples ALPHA1 BRXH REG1,REG3,BETA1 BETA1 BRXLE 1,2,ALPHA1 When assembled, the object code for the instruction labeled ALPHA1, in hexadecimal, is 84130002 where 84 is the operation code 1 is register REG1 3 is register REG3 0002 is the immediate data I2 a value of 2 decimal
APAR Information
APAR number
PN91458
Reported component name
HLASM MVS, VM &
Reported component ID
569623400
Reported release
120
Status
CLOSED UR1
PE
NoPE
HIPER
NoHIPER
Special Attention
YesSpecatt / New Function / Xsystem
Submitted date
1996-11-22
Closed date
1997-01-09
Last modified date
2000-06-15
APAR is sysrouted FROM one or more of the following:
APAR is sysrouted TO one or more of the following:
UN99927 118PC4Ÿ 118PC4Ÿ UN99930 118PC4Ÿ UN99935 118PC4Ÿ UN99934
118PC4Ÿ 118PC4Ÿ
Modules/Macros
$$ERR ASMA28 ASMA29 ASMA5ESA ASMA5UNI ASMA7DE ASMA7EN ASMA7ES ASMA7JP ASMA7UE ASMA9Z OPCODENT OPDEF OPGEN
Fix information
Fixed component name
HLASM MVS, VM &
Fixed component ID
569623400
Applicable component levels
R120 PSY UN99930
UP97/02/11 P F702
R189 PSY UN99927
UP97/02/10 P E221
R320 PSY UN99935
UP97/02/10 P 9702
Fix is available
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Document Information
Modified date:
15 June 2000