Field Programmable Gate Array (FPGA) update requires DC power cycle - Servers

Resolving The Problem

Source

RETAIN tip: H193939

Issue

The system may appear to run with downlevel Field Programmable Gate Array (FPGA) code after updating FPGA.

Expected fixes or new function may not be implemented.

Affected configurations

The system may be any of the following IBM servers:

• System x3850 M2, type 7141, any model
• System x3950 M2, type 7141, any model

This tip is not option specific.

This tip is not software specific.

Workaround

DC power cycle the system or AC power cycle the system.

Additional information

The system must be DC Power Cycled before the new FPGA firmware will become functional. Installation tools provide for an automatic DC Power Cycle, but if the tools are not allowed to run to normal termination, then a manual DC power Cycle is required.

If the Baseboard Management Controller (BMC) is disabled, an AC Power Cycle will be required since the BMC controls the automatic DC Power Cycle FPGA reload function.

FPGA programming tools, which run under Linux or Microsoft Windows, require the operating system to be shut down, and the system manually powered back on so the automatic DC Power Cycle FPGA reload can be run by the BMC. Please be aware that initiating a Restart from within the operating system is not a DC power cycle, and is not sufficient to reload the FPGA with the updated code.

Older systems which used Complex Programmable Logic Devices (CPLD) required an AC power cycle after code updates. FPGA requires only a DC power cycle, although an AC power cycle also implements the updated code.