Troubleshooting
Problem
The following checkpoints can be displayed on the information panel during early stages of the Power-On Self-Test (POST) code.
Resolving The Problem
The following checkpoints can be displayed on the information panel during early portions of the Power-On Self-test (POST) code. If the system hangs with one of these checkpoints displayed, the FRU replacement should be as listed with the first FRU being the first item and so on.
The checkpoint code information is displayed on the information panel in the following format:
CP: 1XX
1XX Checkpoint values as described below.
Notes:
- The checkpoint code will only be displayed by the default ( lowest slot number ) processor card. Therefore, only the default processor card is being tested during this time.
- If a 2 digit checkpoint code (CP: XX) is displayed without a beep symptom, go to 'No Beep Symptoms´ and diagnose the no beep symptom.
- If a 2 digit checkpoint code (CP: XX) is displayed with a beep symptom, go to 'Beep Symptoms´ and diagnose the beep symptom.
| CP code | FRU |
|---|---|
| 141 Start of COM 1 test |
1. System board 2. Bridge card 3. Default processor card |
| 142 Start of SRAM test |
1. Memory card 2. Bridge card 3. Default processor card 4. System board |
| 143 SRAM test |
1. Memory card 2. Default processor card 3. System board |
| 144 SRAM test |
1. Memory card 2. Default processor card 3. System board |
| 145 SRAM test |
1. Memory card 2. Default processor card 3. System board |
| 146 Transition to protected mode |
1. Default processor card 2. Bridge card 3. System board |
| 147 Port initialization |
1. Default processor card 2. Bridge card 3. System board |
| 148 Jump to 32-Bit assembly code |
1. Default processor card 2. Bridge card 3. Memory card 4. System board |
| 149 Execution of 32-Bit protected mode |
1. Default processor card 2. Bridge card 3. Memory card 4. System board |
| 14A Transition to 'C' code |
1. Default processor card 2. Bridge card 3. System board |
| 14C Default processor card setup routines |
1. Default processor card 2. Bridge card 3. System board |
| 14D Additional default processor card setup routines |
1. Default processor card 2. Bridge card 3. System board |
| 14E Additional default processor card setup routines |
1. Default processor card 2. Bridge card 3. System board |
| 14F Additional default processor card setup routines |
1. Default processor card 2. Bridge card 3. System board |
| 150 ROM Checksum |
1. System board 2. Bridge card 3. Default processor card |
| 151 L2 Cache flush on default processor card |
1. Default processor card 2. Bridge card 3. Memory card 4. System board |
| 152 Default processor card configuration |
1. Default processor card 2. Bridge card 3. System board |
| 153 Default processor card and bridge card initialization |
1. Default processor card 2. Bridge card 3. System board |
| 154 Bridge DMA initialization |
1. Bridge card 2. System board 3. Default processor card 4. Memory card |
| 155 Enable fault/error detection and enable interrupts |
1. Default processor card 2. Bridge card 3. System board |
| 156 Enable default processor card parity and L1 Cache |
1. Default processor card 2. Bridge card 3. System board 4. Memory card |
| 157 Start of test cases |
1. Default processor card 2. Bridge card 3. System board |
| 158 Video initialization |
1. Default processor card 2. System board 3. Bridge card |
| 159 Keyboard initialization |
1. Keyboard 2. System board |
| 15A Global initialization. Try removing the wrap plug from the serial port. |
1. System board 2. Default processor card |
In some cases, the early POST code will detect errors during the running of the test cases and display corresponding test errors to the information panel. The information is displayed in the following format:
EP: 1XXS
1XX Error values as described below.
S Slot number of the card/board issuing the error.
| EP code | FRU |
|---|---|
| 1043 (104X) Memory error (First reseat the memory adapter.) |
1. Memory adapter |
| 106s Processor card error |
1. Processor card |
Document Location
Worldwide
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Document Information
Modified date:
23 January 2019
UID
ibm1BJON-3QHCGJ