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PH69536: QR TCB HUNG AFTER CICS ENABLED DBCTL WITHOUT OPENAPI

A fix is available

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APAR status

  • Closed as program error.

Error description

  • You have OPENTHRD(CCTL) set in DRA Startup Parameters in IMS.
    
    DFHDBCON enables the DBCTL TRUE with 2 EXEC CICS ENABLEs.  When
    the first ENABLE is done, neither QUASIRENT nor OPENTHREAD are
    specified.   After enabling the TRUE, it does an initial call to
    the TRUE (and IMS) to connect.  When that comes back, it knows
    whether or not OPENTHREAD is specified in DRA Startup Table.
    Then it can do another ENABLE to specify QUASIRENT or OPENAPI.
    
    
    
    But there is potentially a 1 second delay between those 2
    ENABLEs. In this situation, during that 1-second delay, before
    the DBCTL TRUE is Enabled with OPENAPI.   application
    transactions arrive and use the IMS-DBCTL interface.   It all
    happens on the QR TCB, including in IMS proper.  The
    transactions each do 1 CALLDLI call, then each does a 1-second
    delay while holding the DBCTL thread.   Eventually this either
    results in a QR-TCB hang in IMS or an abend32E.
    

Local fix

Problem summary

  • ****************************************************************
    * USERS AFFECTED: All CICS users                               *
    ****************************************************************
    * PROBLEM DESCRIPTION: DLI requests can be processed in IMS    *
    *                      under the QR TCB, leading to SVC 1      *
    *                      WAITs, or abend32E with msg "DFHDS0001  *
    *                      An abend (code 32E/AKEB) has occurred   *
    *                      at offset X'FFFF' in module DFHDSDS3."  *
    ****************************************************************
    The CDBC transaction connects CICS to IMS via DBCTL. If it is
    driven as part of sequential terminal input, other transactions
    can be attached to run at the same time as DFHDBCON completes
    the connection work.
      DFHDBCON issues two EXEC CICS ENABLE commands for the TRUE,
    and CICS will delay the connection process between these to
    allow for sequential terminal processing requirements. CICS does
    not know whether IMS expects work to be handled under open TCBs
    or the QR TCB until this delay has completed. Before this time,
    the connection will default to using QR, even if the IMS DRA
    has specified OPENTHRD(CCTL) meaning IMS is to be called to
    perform its work under L8 TCBs.
      CICS transactions may perform IMS work before the delay has
    completed and the second ENABLE command set the correct OTE
    parameters (THREADSAFE OPENAPI). IMS is called under QR to
    perform this work, but IMS does not invoke the DFHDBSPX exit
    to allow CICS to dispatch other transactions.
      Depending on the environment, the QR TCB may enter an SVC 1
    WAIT, or abend 32E due to a lack of STIMERM slots. It may also
    successfully process the request and produce no obvious error
    (that is, no DFHDS0001 error message be issued).
    

Problem conclusion

  • CICS has been modified to disallow work against IMS while in
    the delay for sequential terminal processing within DFHDBCON.
    Any such work that attempts to run will now abend ADCJ.
    
      CICS Data Areas will be updated to define a new bit within the
    DFHDGB control block. The reserved halfword at x3E will be
    redefined as follows for CICS TS 6.1, 6.2 and 6.3:
    (3E) CHARACTER       1   DGBFLAGS  Flag byte
    (3E) 1...  ....          DGBDELAY  DFHDBCON is in a DELAY
    (3E) .111  1111          *         Reserved
    (3F) CHARACTER       1   *         Reserved
    .
    The CICS documentation will be updated to reflect this.
    

Temporary fix

Comments

APAR Information

  • APAR number

    PH69536

  • Reported component name

    CICS TS Z/OS V6

  • Reported component ID

    5655YA100

  • Reported release

    400

  • Status

    CLOSED PER

  • PE

    NoPE

  • HIPER

    NoHIPER

  • Special Attention

    NoSpecatt / Xsystem

  • Submitted date

    2026-01-05

  • Closed date

    2026-04-22

  • Last modified date

    2026-05-02

  • APAR is sysrouted FROM one or more of the following:

  • APAR is sysrouted TO one or more of the following:

    UO07562 UO07563 UO07564

Modules/Macros

  • DFHDBCON DFHDBUDS DFHDLIDP DFHDLP
    

Fix information

  • Fixed component name

    CICS TS Z/OS V6

  • Fixed component ID

    5655YA100

Applicable component levels

  • R400 PSY UO07564

       UP26/04/29 P F604

  • R500 PSY UO07563

       UP26/04/29 P F604

  • R600 PSY UO07562

       UP26/04/29 P F604

Fix is available

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Document Information

Modified date:
02 May 2026