OW22157: APPLS HANG WHEN ISSUING SVC WHILE THE PROCESS-MUST-COMPLETE BIT IS SET. 96/08/21 PTF PECHANGE

Obtain the fix for this APAR.

APAR status

• Closed as program error.

Error description

• VTAM APPLs hang when issuing an SVC in process-must-complete
  mode.  STATUS RESET,MC,PROCESS was not getting issued.
  OW17421 introduced the error where VTAM turned on the process
  must complete bit but did not turn it off.
  ****
  The APPL will hang with the local lock held by a task suspended
  in status at label CMLGONE in IEAVSETS (IGC079). REG10 points
  to the TCB we're waiting on and the TCB will have TCBPMC on.
  The TCB will be in a wait and that in conjuction with having
  TCBPMC on hangs the APPL.  (TCBPMC is on if TCB+X'117'= X'80')
  Additional symptom:  ABEND0C4 ISTAICIO +x'3A6' on a test under
  mask instruction, 91209013, and the storage pointed to by reg9
  is not available.  The translation exception address is on the
  page of storage that reg9 points to.
  

Local fix

• Call the VTAM support center for a temporary fix.
  

Problem summary

• ****************************************************************
  * USERS AFFECTED: All customers with UW26276 (201) or          *
  *                 UW26278 (301) applied.                       *
  ****************************************************************
  * PROBLEM DESCRIPTION: Application hangs due to issuing an SVC *
  *                      while in Process Must Complete mode.    *
  ****************************************************************
  * RECOMMENDATION:                                              *
  ****************************************************************
  The problem is described as follows:
  1) OW17421 addresses the problem of a VTAM hang when a macro-
     instruction is issued synchronously within an ACB exit.
  2) To resolve the VTAM hang, OW17421 utilized an MVS mechanism
     to stop interrupts during TCB Authorized mode API
     processing.
  3) The MVS mechanism is a STATUS macro that can SET the mode
     to PROCESS MUST COMPLETE which will stop interrupts until
     the mode is RESET. ((TCBPMC=ON (SET), TCBPMC=OFF (RESET))
  4) While in PROCESS MUST COMPLETE mode, SVCs are not allowed.
  5) In mainline API processing the STATUS macro is invoked if
     the RPL is TCB authorized mode.
  6) Later in the processing (in some cases), the RPL is TPQUE'd
     to another PAB for processing.
  7) The latter PAB processing can lead to the posting of the RPL
     running via an SRB exit.
  8) When processing is returned to mainline, if the RPL indicates
     authorized and running under a TCB then the STATUS macro is
     invoked to RESET the mode.
  9) As #7 processing has occurred, the RPL indicator is
     unpredictable.
  10)Due to the authorized indicator being off, Process Must
     Complete mode is not reset.
  11)So when the address space issues an SVC the address space
     hangs. (SVC-entered WAIT while in Process Must Complete mode)
  

Problem conclusion

• To resolve the problem, ISTAICIO will set a local bit (MCSET),
  when Process Must Complete mode is set. When processing is
  returned to mainline, if MCSET is on then the mode will be
  reset. (No longer dependent on an RPL indicator that could
  change).
  

Temporary fix

• *********
  * HIPER *
  *********
  

Comments

APAR Information

• APAR is sysrouted FROM one or more of the following:

• APAR is sysrouted TO one or more of the following:

  UW31882 UW31883

Modules/Macros

• ISTAICIO
  

Fix information

• Fixed component name

  VTAM V4 MVS/ESA

• Fixed component ID

  569511701

Applicable component levels

• R201 PSY UW31882

     UP96/09/26 P F609 «

• R301 PSY UW31883

     UP96/09/26 P F609 «

Fix is available

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