CTCS_HOOKx Macros

Purpose

Record a trace event into component serialized Component Trace, Lightweight Memory Trace (LMT), or system trace buffers.

Syntax

The following set of macros is provided to record a trace entry:

#include <sys/ras_trace.h>
CTCS_HOOK0(ras_block_t cb, int level, int mem_dest, long hkwd);
CTCS_HOOK1(ras_block_t cb, int level, int mem_dest, long hkwd, long d1);
CTCS_HOOK2(ras_block_t cb, int level, int mem_dest, long hkwd, long d1, long d2);
CTCS_HOOK3(ras_block_t cb, int level, int mem_dest, long hkwd, long d1, long d2, long d3);
CTCS_HOOK4(ras_block_t cb, int level, int mem_dest, long hkwd, long d1, long d2, long d3, long d4);
CTCS_HOOK5(ras_block_t cb, int level, int mem_dest, long hkwd, long d1, long d2, long d3, long d4, 
long d5);

Description

The CTCS_HOOKx macros record a trace hook in to a Component Trace buffer that is component-serialized. These macros cannot be used with buffers that are not component-serialized. The x in CTCS_HOOKx is the number of data words you want in this trace event.

All of the traces that are recorded are time-stamped.

If the cb input parameter contains a value of RAS_BLOCK_NULL, no tracing is performed.

Parameters

Item	Description
ras_block_t cb	The cb parameter is the RAS control block that links to the component that this trace entry belongs to.
int level	The level parameter allows filtering of different trace entries. The higher this level is, the more this trace is considered as debug or detail information. This trace entry is displayed only if the level of the trace entry is less than or equal to the level of the trace chosen for memory or system trace mode. Ten levels of trace are available (CT_LEVEL_0 to CT_LEVEL_9, corresponding to value 0 to 9) with the following special levels: Minimal (CT_LVL_MINIMAL (=CT_LEVEL_1)) Normal (CT_LVL_NORMAL (=CT_LEVEL_3)) Detail (CT_LVL_DETAIL (=CT_LEVEL_7)) Default (CT_LVL_DEFAULT = CT_LVL_NORMAL in AIX® 6.1 and above. Otherwise, it is CT_LVL_MINIMAL) When you are porting an existing driver or subsystem from the existing system trace to a component trace, existing entries should be traced at the CT_LVL_DEFAULT level.
int mem_dest	The mem_dest parameter indicates the memory destination for this trace entry. It is an ORed value with the following possible settings: MT_RARE The trace entry is saved in the rare buffer of lightweight memory. In this case, the current level of trace for the memory trace mode is greater than or equal to the level of this trace entry. MT_COMMON The trace entry is saved in the common buffer of the lightweight memory trace. MT_PRIV The trace entry is saved in the private memory buffer of the component. MT_SYSTEM The trace entry is saved in the existing system trace if all of the following conditions are true: The level condition of the system trace mode for this control block is satisfied The system trace is running The hook meets any additional criteria specified as part of the system trace If MT_SYSTEM is not set, the trace entry is not saved in the existing system trace. Only one of the MT_RARE, MT_COMMON, and MT_PRIV values should be used, but you can combine ORed with MT_SYSTEM. Otherwise, the trace entry will be duplicated in several memory buffers. The mem_dest parameter is not necessary for the CT_GEN macro because Lightweight Memory Trace cannot accommodate generic entries. The CT_GEN macro checks the memory trace and system trace levels to determine whether the generic entry should enter the private memory buffer and the system trace buffers respectively.

Item

Description

ras_block_t cb

The cb parameter is the RAS control block that links to the component that this trace entry belongs to.

int level

The level parameter allows filtering of different trace entries. The higher this level is, the more this trace is considered as debug or detail information. This trace entry is displayed only if the level of the trace entry is less than or equal to the level of the trace chosen for memory or system trace mode.

Ten levels of trace are available (CT_LEVEL_0 to CT_LEVEL_9, corresponding to value 0 to 9) with the following special levels:

Minimal (CT_LVL_MINIMAL (=CT_LEVEL_1))
Normal (CT_LVL_NORMAL (=CT_LEVEL_3))
Detail (CT_LVL_DETAIL (=CT_LEVEL_7))
Default (CT_LVL_DEFAULT = CT_LVL_NORMAL in AIX® 6.1 and above. Otherwise, it is CT_LVL_MINIMAL)

When you are porting an existing driver or subsystem from the existing system trace to a component trace, existing entries should be traced at the CT_LVL_DEFAULT level.

int mem_dest

The mem_dest parameter indicates the memory destination for this trace entry. It is an ORed value with the following possible settings:

MT_RARE

The trace entry is saved in the rare buffer of lightweight memory. In this case, the current level of trace for the memory trace mode is greater than or equal to the level of this trace entry.

MT_COMMON

The trace entry is saved in the common buffer of the lightweight memory trace.

MT_PRIV

The trace entry is saved in the private memory buffer of the component.

MT_SYSTEM

The trace entry is saved in the existing system trace if all of the following conditions are true:

The level condition of the system trace mode for this control block is satisfied
The system trace is running
The hook meets any additional criteria specified as part of the system trace

If MT_SYSTEM is not set, the trace entry is not saved in the existing system trace.

Only one of the MT_RARE, MT_COMMON, and MT_PRIV values should be used, but you can combine ORed with MT_SYSTEM. Otherwise, the trace entry will be duplicated in several memory buffers.

The mem_dest parameter is not necessary for the CT_GEN macro because Lightweight Memory Trace cannot accommodate generic entries. The CT_GEN macro checks the memory trace and system trace levels to determine whether the generic entry should enter the private memory buffer and the system trace buffers respectively.

The hkwd, d1, d2, d3, d4, and d5 parameters are the same as those used for the existing TRCHKx macros. The TRCHKx macros link to the TRCHKLnT macros where n is from 0 to 5. For example, TRCHKL1T (hkwd, d1).