tlbli (Load Instruction TLB Entry) instruction

Edit online

Purpose

Loads the instruction Translation Look-Aside Buffer (TLB) entry to assist a TLB reload function performed in software on the PowerPC 603 RISC Microprocessor.

Note:
  1. The tlbli instruction is supported only on the PowerPC 603 RISC Microprocessor. It is not part of the PowerPC architecture and not part of the POWER family architecture.
  2. TLB reload is usually done by the hardware, but on the PowerPC 603 RISC Microprocessor this is done by software.
  3. When AIX is installed on a system using the PowerPC 603 RISC Microprocessor, software to perform the TLB reload function is provided as part of the operating system. You are likely to need to use this instruction only if you are writing software for the PowerPC 603 RISC Microprocessor intended to operate without AIX.

Syntax

Bits Value
0 - 5 31
6 - 10 ///
11 - 15 ///
16 - 20 RB
21 - 30 1010
31 /
Item Description
PowerPC 603 RISC Microprocessor PowerPC 603 RISC Microprocessor
tlbli RB

Description

For better understanding, the following information is presented:

  • Information about a typical TLB reload function that would call the tlbli instruction.
  • An explanation of what the tlbli instruction does.

Typical TLB Reload Function

In the processing of the address translation, the Effective Address (EA) is first translated into a Virtual Address (VA). The part of the Virtual Address is used to select the TLB entry. If an entry is not found in the TLB, a miss is detected. When a miss is detected, the EA is loaded into the instruction TLB Miss Address (IMISS) register. The first word of the target Page Table Entry is loaded into the instruction TLB Miss Compare (ICMP) register. A routine is invoked to compare the content of ICMP with all the entries in the primary Page Table Entry Group (PTEG) pointed to by the HASH1 register and with all the entries in the secondary PTEG pointed to by the HASH2 register. When there is a match, the tlbli instruction is invoked.