Functional differences for POWER® family and PowerPC® instructions
The POWER® family and PowerPC® instructions that share the same op code on POWER® family and PowerPC® platforms, but differ in their functional definition.
The following table lists the POWER® family and PowerPC® instructions that share the same op code on POWER® family and PowerPC® platforms, but differ in their functional definition. Use caution when using these instructions in com assembly mode.
| POWER® family | PowerPC® | Description |
|---|---|---|
| dcs | sync | The sync instruction causes more pervasive synchronization in PowerPC® than the dcs instruction does in POWER® family. |
| ics | isync | The isync instruction causes more pervasive synchronization in PowerPC® than the ics instruction does in POWER® family. |
| svca | sc | In POWER® family, information from MSR is saved into CTR. In PowerPC®, this information is saved into SRR1. PowerPC® only supports one vector. POWER® family allows instruction fetching to continue at any of 128 locations. POWER® family saves the low-order 16 bits of the instruction in CTR. PowerPC® does not save the low-order 16 bits of the instruction. |
| mtsri | mtsrin | POWER® family uses the RA field to compute the segment register number and, in some cases, the effective address (EA) is stored. PowerPC® has no RA field, and the EA is not stored. |
| lsx | lswx | POWER® family does not alter the target register RT if the string length is 0. PowerPC® leaves the contents of the target register RT undefined if the string length is 0. |
| mfsr | mfsr | This is a nonprivileged instruction in POWER® family. It is a privileged instruction in PowerPC®. |
| mfmsr | mfmsr | This is a nonprivileged instruction in POWER® family. It is a privileged instruction in PowerPC®. |
| mfdec | mfdec | The mfdec instruction is nonprivileged in POWER® family, but becomes a privileged instruction in PowerPC®. As a result, the DEC encoding number for the mfdec instruction is different for POWER® family and PowerPC®. |
| mffs | mffs | POWER® family sets the high-order 32 bits of the result to 0xFFFF FFFF. In PowerPC®, the high-order 32 bits of the result are undefined. |
See Features of the AIX® assembler for more information on the PowerPC®-specific features of the assembler.