svc (Supervisor Call) instruction

Purpose

Generates a supervisor call interrupt.

Note: The svc instruction is supported only in the POWER® family architecture.

Syntax

Description

The svc instruction generates a supervisor call interrupt and places bits 16-31 of the svc instruction into bits 0-15 of the Count Register (CR) and bits 16-31 of the Machine State Register (MSR) into bits 16-31 of the CR.

Consider the following when using the svc instruction:

• If the SVC Absolute bit (SA) is set to 0, the instruction fetch and execution continues at one of the 128 offsets, b'1'|| LEV ||b'00000', to the base effective address (EA) indicated by the setting of the IP bit of the MSR. FL1 and FL2 fields could be used for passing data to the SVC routine but are ignored by hardware.
• If the SVC Absolute bit (SA) is set to 1, then instruction fetch and execution continues at the offset, x'1FE0', to the base EA indicated by the setting of the IP bit of the MSR.
• If the Link bit (LK) is set to 1, the EA of the instruction following the svc instruction is placed in the Link Register.

  Notes:

  1. To ensure correct operation, an svc instruction must be preceded by an unconditional branch or a CR instruction. If a useful instruction cannot be scheduled as specified, use a no-op version of the cror instruction with the following syntax:

     
     cror BT,BA,BB      No-op when BT = BA = BB
     

  2. The svc instruction has the same op code as the sc (System Call) instruction.

The svc instruction has four syntax forms. Each syntax form affects the MSR.

The four syntax forms of the svc instruction never affect the FP, ME, AL, IP, IR, or DR bits of the MSR. The EE, PR, and FE bits of the MSR are always set to 0. The Fixed-Point Exception Register and Condition Register Field 0 are unaffected by the svc instruction.

Parameters