ARCHITECTURE

• 9021-520, 9021-640, 9021-660, 9021-740, 9021-820, 9021-860, and 9021-900
• 9021-xx1 and 9021-xx2
• 9672-Rx1, 9672-Rx2 (G1), 9672-Exx, and 9672-Pxx

Specifically, these ARCH(1) machines and their follow-ons add the C Logical String Assist hardware instructions. These instructions are exploited by the compiler, when practical, for a faster and more compact implementation of some functions, for example, strcmp().

• 9672-Rx3 (G2), 9672-Rx4 (G3), 9672-Rx5 (G4), and 2003

Specifically, these ARCH(2) machines and their follow-ons add the Branch Relative instruction (Branch Relative and Save - BRAS), and the halfword Immediate instruction set (for example, Add Halfword Immediate - AHI) which may be exploited by the compiler for faster processing.

Specifically, these ARCH(3) machines and their follow-ons add a set of facilities for IEEE floating-point representation, as well as 12 additional floating-point registers and some new floating-point support instructions that may be exploited by the compiler.

Note that ARCH(3) is required for execution of a program that specifies the FLOAT(IEEE) compiler option. However, if the program is executed on a physical processor that does not actually provide these ARCH(3) facilities, any program check (operation or specification exception), resulting from an attempt to use features associated with IEEE floating point or the additional floating point registers, will be intercepted by the underlying operating system, and simulated by software. There will be a significant performance degradation for the simulation.

Specifically, the following instructions are used for long long operations:

• 32-bit Add-With-Carry (ALC, ALCR) for long long addition (rather than requiring a branch sequence)
• 32-bit Subtract-With-Borrow (SLB, SLBR) for long long subtraction (rather than requiring a branch sequence)
• Inline sequence with 32-bit Multiply-Logical (ML, MLR) for long long multiplication (rather than calling @@MULI64)

Specifically, ARCH(5) is the minimum requirement for execution of a program in 64-bit mode. If you explicitly set ARCH to a lower level, the compiler will issue a warning message and ignore your setting. ARCH(5) specifies the target machine architecture and the application can be either 31-bit or 64-bit.

Specifically, these ARCH(6) machines and their follow-ons add the long-displacement facility. For further information on the long-displacement facility, refer to z/Architecture Principles of Operation.

Specifically, these ARCH(7) machines and their follow-ons add instructions supported by the extended-immediate facility, which may be exploited by the compiler. Also, these machines add instructions supported by the decimal floating-point facility, which are generated if the DFP compiler option is specified and there are decimal floating-point data types in the source code. For further information on these facilities, refer to z/Architecture Principles of Operation.

Specifically, these ARCH(8) machines and their follow-ons add instructions supported by the general instruction extensions facility, which may be exploited by the compiler. Also, these machines improve the performance of instructions that are supported by the decimal floating-point facility, which are generated if the DFP compiler option is specified and there are decimal floating-point data types in the source code. For further information on these facilities, refer to z/Architecture Principles of Operation.

Specifically, these ARCH(9) machines and their follow-ons add instructions supported by the high-word facility, the interlocked-access facility, the load/store-on-condition facility, the distinct-operands-facility and the population-count facility. For further information about these facilities, see z/Architecture Principles of Operation.

Specifically, these ARCH(10) machines and their follow-ons add instructions supported by the execution-hint facility, the load-and-trap facility, the miscellaneous-instruction-extension facility, and the transactional-execution facility. For further information about these facilities, see z/Architecture Principles of Operation.

Specifically, these ARCH(11) machines and their follow-ons add instructions supported by the vector facility, the decimal floating point packed conversion facility, and the load/store-on-condition facility 2. The VECTOR option is required for the compiler to use the vector facility. For further information about these facilities, see z/Architecture Principles of Operation.

and the 3907-xxx (IBM z14 Model ZR1)

Specifically, these ARCH(12) machines and their follow-ons add instructions supported by the vector enhancement facility 1, the vector packed decimal facility, and the miscellaneous instruction extension facility 2. The VECTOR option is required for the compiler to use the vector enhancement facility 1 and vector packed decimal facility. For further information about these facilities, see z/Architecture Principles of Operation.

Specifically, these ARCH(13) machines and their follow-ons add instructions supported by the vector enhancement facility 2, vector packed decimal enhancement facility, and the miscellaneous instruction extensions facility 3. For further information about these facilities, see z/Architecture Principles of Operation.