Using the BASSM and BSM instructions

The BASSM (branch and save and set mode) and the BSM (branch and set mode) instructions are branching instructions that set the addressing mode. They are designed to complement each other. (BASSM is used to call and BSM is used to return, but they are not limited to such use.)

The description of BASSM appears in Figure 1. (See Principles of Operation for more information.)
Figure 1. BRANCH and SAVE and Set Mode Description
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Bits 32-63 of the current PSW, including the updated instruction address, are saved as link information in the general register designated by R1. Subsequently, the addressing mode and instruction address in the current PSW are replaced from the second operand. The action associated with the second operand is not performed if the R2 field is zero.

The contents of the general register designated by the R2 field specify the new addressing mode and branch address; however when the R2 field is zero, the operation is performed without branching and without setting the addressing mode.

When the contents of the general register designated by the R2 field are used, bit 0 of the register specifies the new addressing mode and replaces bit 32 of the current PSW, and the branch address is generated from the contents of the register under the control of the new addressing mode. The new value for the PSW is computed before the register designated by R1 is changed.

Condition Code: The code remains unchanged.

Program Exceptions: Trace (R2 field is not zero).

The description of BSM appears in Figure 2. (See Principles of Operation for more information.)
Figure 2. Branch and Set Mode Description
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Bit 32 of the current PSW, the addressing mode, is inserted into the first operand. Subsequently the addressing mode and instruction address in the current PSW are replaced from the second operand. The action associated with an operand is not performed if the associated R field is zero.

The value of bit 32 of the PSW is placed in bit position 0 of the general register designated by R1, and bits 1-31 of the register remain unchanged; however, when the R1 field is zero, the bit is not inserted, and the contents of general register 0 are not changed.

The contents of the general register designated by the R2 field specify the new addressing mode and branch address; however, when the R2 field is zero, the operation is performed without branching and without setting the addressing mode.

When the contents of the general register designated by the R2 field are used, bit 0 of the register specifies the new addressing mode and replaces bit 32 of the current PSW, and the branch address is generated from the contents of the register under the control of the new addressing mode. The new value for the PSW is computed before the register designated by R1 is changed.

Condition Code: The code remains unchanged.

Program Exceptions: None.