When LINKAGE=SYSTEM is specified

Start of change The ERRET routine is given control in the issuer's primary address space. End of change

The routine executes in supervisor state and PSW key 0. It receives control enabled, unlocked, in SRB mode, and with the following register contents:

Register: Contents
0: ECB address
1: ASCB address (address specified for ASCB keyword)
2: completion code specified on POST invocation
3: system completion code that indicates why the POST request failed
4-13: used as a work register by the system
14: return address
15: ERRET address

The ERRET routine will receive control in the addressing mode of the caller of the cross memory POST, and the ERRET routine will run in a cross memory environment where home, primary, and secondary address spaces are all equal. The ERRET routine must return control to the address in register 14, unlocked and enabled.

If cross-memory post is being used, a synchronization problem arises when it becomes necessary to eliminate an ECB that is a potential target for a cross memory post request. To ensure that all outstanding cross memory post requests for the ECB have completed, the user must invoke the SPOST macro. The ECB might or might not be posted, depending on existing conditions.