Branch entry to the POST service routine provides, through LINKAGE=BRANCH,
all the normal ECB and RB POST processing. To use the entry points,
shown in Table 1, you must write your own code. In general,
the caller must hold the LOCAL lock and be in supervisor state, PSW
key zero. Upon completion of the POST process, control returns to
the caller in supervisor state, PSW key zero with the LOCAL lock.
Note: CML (cross memory local) lock means the local lock of an address
space other than the home address space. LOCAL lock means the local
lock of the home address space. When written in lower case, local
lock means any local-level lock, either the local or a CML lock.
You can use branch entry to the POST service routine in cross memory
mode for cross memory POST. If you hold the LOCAL lock
of the home address space and if bit 0 of register 12 is 0, then the
current address space must be the home address space and registers
0-9 and 14 are preserved. If you do not hold home's LOCAL lock or
if bit 0 of register 12 is 1, then the current address space can be
any address space and only registers 9 and 14 are preserved.
Note: If the high-order bit of register 12 is 0 and an error routine
is invoked, the error routine is dispatched in the home address space.
The error routine is also dispatched in the home address space when
you use MEMREL=YES on the POST macro. However, if the high-order bit
of register 12 is 1 (which is equivalent to coding MEMREL=NO on a
POST macro), then the error routine is dispatched in ASID 1.
Table 1 shows the POST function and the
branch entry points through which those functions can be performed.
Table 2 shows the input parameters to POST.
Table 3 shows the output parameters from POST.
Table 1. POST Function and Branch Entry
Points| Functions |
|
Entry Points |
|
|
|---|
| |
LINKAGE=BRANCH |
CVT0PT02 |
CVT0PT03* |
CVT0PT0E |
| Local ECB POST |
X |
X |
X |
|
| Cross memory POST |
X** |
|
X |
|
| Post exit creation/deletion |
|
|
|
X |
- *
- This entry point performs processing identical to entry point
POST macro linkage=BRANCH. It is designed for use only by POST exit
routines (that is, routines that receive control from POST as the
result of having established that exit via entry point CVT0PT0E).
- **
- The local lock does not need to be held for a cross memory POST
at this entry point.
Table 2. POST Branch Entry Input| Registers |
CVT0PT02 |
CVT0PT03 |
CVT0PT0E |
|---|
| 0 |
|
ECB storage protect key(1) |
Function Code |
| 1 |
|
|
Exit Routine Address |
| 10 |
Completion Code |
Completion Code(2) |
|
| 11 |
ECB Address |
ECB Address(3) |
|
| 12 |
|
Error Routine
Address(4)
|
|
| 13 |
|
ASCB Address(4) |
|
| 14 |
Return Address |
Return Address |
Return Address |
| 15 |
Entry Point Address |
Entry Point Address |
Entry Point Address |
Note: - If cross memory post, optionally contains the storage protection
key of the ECB in bits 24-27.
- If cross memory post and the storage protection key of the ECB
is supplied in register 0, then the high order bit must be set to
one.
- If local POST, ensure high order bit of register is zero; if cross
memory POST, set high-order bit of register to 1.
- Only necessary when performing cross memory POST. If performing
a cross memory POST and the high order bit in register 12 is on, only
registers 9 and 14 are retained, and the error routine executes in
the master scheduler's address space.
Table 3. POST Branch Entry Output| Entry Points/Options |
Registers Saved and Restored |
|---|
| LINKAGE=BRANCH and ASCB not specified |
0-9, 12, 13 |
LINKAGE=BRANCH and ASCB specified - Local lock held and MEMREL=YES
- Local lock not held or MEMREL=NO
|
0-9
9
|
| CVT0PT02 |
0-9, 12-14 |
| CVT0PT03 |
0-14 |
| CVT0PT0E |
2-14 |