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Program-Controlled Interruption Appendage z/OS DFSMSdfp Advanced Services SC23-6861-01 |
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This appendage is entered if the channel finds one or more program-controlled-interruption (PCI) bits on in a channel program. It can be entered as many times as the channel finds PCI bits on, or more often. Before the appendage is entered, the contents of the subchannel status word are placed in the channel status word field of the input/output block. Note that PCI and PCI appendages are not supported for zHPF channel programs. A PCI appendage is reentered if an ERP is retrying a channel program in which a PCI bit is on. The IOB error flag is set when the ERP is in control (IOBFLAG1 = X'20'). (For special PCI conditions encountered with command retry, see Command Retry Considerations.) To post the channel program from a PCI appendage to an EXCP request (EXCP V=V), use the procedure described in SIO Appendage. If the step is running ADDRSPC=REAL (V=R) and an authorized program issued the EXCP request or if an EXCPVR request was issued, the PCI appendage uses central storage addresses. Use the following procedure to post the channel program from the PCI appendage. For more information on the POST macro, see z/OS MVS Programming: Authorized Assembler Services Guide and z/OS MVS Programming: Authorized Assembler Services Reference LLA-SDU. The POST macro is coded as follows:
The ERRET routine address
must point to a BR 14 instruction. This instruction must be in storage
addressable from any address space (for example, CVTBRET) and addressable
by 24 bits.Note: If you specify the ASCB parameter with MEMREL=NO, only registers
9 and 14 are restored when returning from the POST macro.
The following procedure posts the channel program from the PCI appendage.
To return control to the system for normal operation, use the return address in register 14. |
Copyright IBM Corporation 1990, 2014
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