KERRD - Kernel error data

      CONTROL BLOCK NAME = DFHKERRD
      MATCHING ASSEMBLER CONTROL BLOCK = DFHKERN TYPE=ERROR_DATA
      DESCRIPTIVE NAME = CICS TS Kernel Error Data
           Licensed Materials - Property of IBM
            Restricted Materials of IBM 
           5655-Y04
           (C) Copyright IBM Corp. 1988, 2012 
      FUNCTION = Kernel Error Data.
      After an MVS Abend, Program Check or Domain Requested Recovery,
      The following data is available to the task in recovery state.
      Once the recovery state is cleared or percolated, this data is
      no longer available.
      The data splits into three parts:
      1. Error Code and Interrupt information.
         The Error Code is supplied on a CICS Request Recovery Call
         and is a CICS Abend Code (as documented in CICS Messages
         and Codes).
         If the Error Code is AKEA then there has been a program
         check and the System Interrupt data will be the program
         check code ( 00CX ).
         If the Error Code is AKEB then there has been an MVS Abend
         and then System and User Interrupt data will contain the
         MVS Abend Code split up into the System and User parts.
         The Kernel will calculate the offset within your program
         that the CICS error occurred. If not in your program, this
         field is set negative.
      2. SYSTEM Error Data - PSW and Registers taken from the SDWA.
         SDWA:  PSW and Registers at time of error. 
         There are two sets of PSW and Registers, which are different
         when CICS has called an SVC (say) which then issues an
         Abend. In this case the phrase 'at time of error' indicates
         that this set of PSW and Registers will be those of the
         SVC: the PSW will be the address (in the SVC routine)
         of an Abend SVC (13).
      3. CICS Error Data - PSW and Registers taken from the SDWA.
         SDWA: "PSW and Registers of last interrupt of the RB that
                 issued this STAE/ESTAE. 
         This is a rather cryptic phrase. Remember, however, that
         the RB that issued the ESTAE is actually CICS and that,
         since CICS does not issue LINK, CICS only ever has the one
         RB EXCEPT when we issue an SVC.
         S370 hardware implements SVC's and Program Checks as
         interrupts. Thus, if CICS issues an SVC that then abends,
         the last interrupt we received WAS the SVC. So, this
         save area describes the last thing CICS did before the
         Abend.
      Notes
      1. If CICS issues an Abend (or program checks) from its
         own code, these two save areas are identical and identify
         the place where the Abend or program check happenned.
      2. In the case of requested recovery, both sets of PSW and
         Registers will identify the state at the time the request
         recovery was issued.
      3. When the Abend is issued from 'the System', the two save
         areas are used for different purposes.
         If the problem is to diagnose what VTAM/VSAM/MVS/etc. was
         doing for us at the time, the approriate Error Data is the
         SYSTEM's, since that tells us what the state was on that
         side of the SVC.
         If the problem is to diagnose an invalid request made by
         CICS, then the last thing CICS did is relevant and so the
         CICS Error Data is relevant.
      NOTES :
       DEPENDENCIES = S/370
       RESTRICTIONS = None
       MODULE TYPE = Control block definition

     For some unknown reason the compile does not like the statement
     below. DFHPGRE has about a hundred compile errors with it
     but all the other modules in mpu UAPV are happy with it
     To overcome the problem I've put KERNEL_ERROR_REASON
     in a structure
     2 PTR, Reserved - 64 bit

         The following 2 fields are only valid if
         KERNEL_ERROR_IN_SUBSPACE is set

     Kernel Error Type: Value Definitions.

    Kernel Error Executing RB : Test value
       - Error occurred in CICS RB if:
                not in SRB mode,
                no IRB in RB stack,
            and CICS RB was in control.