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Announced Aug 2, 1972 and
withdrawn Sep 15, 1980The Model 168 gained its power largely from a combination of (1) ultra-high-speed buffer storage, (2) operation of the instruction unit's logic circuitry, which capitalized on the availability of instructions and data from the buffer, and (3) a high degree of concurrency in operation. The operation of the instruction unit was overlapped, allowing up to three instructions to be undergoing preparation concurrently so that the next program-sequenced instruction was ready for execution. Introduced with the 168 were an additional register and instruction buffer to increase overlap, and reorganization of the optional 16K buffer to gain speed.

New or extended features of the Model 168 were designed for high availability, eased application development, and operational flexibility, with emphasis on the needs of large data base and data communications systems. They also were designed for more flexible growth paths to meet the needs of application development and changing workloads. These features included virtual storage and multiprocessing capabilities and the availability of up to eight megabytes of integrated monolithic processor storage with a Model 168.

• Extended control mode of system operation, dynamic address translation, and channel indirect data addressing--features required for the implementation of virtual storage
• Two types of multiprocessing support
• Up to eight megabytes of monolithic processor (main) storage with a single Model 168
• New optional 3068 Multisystem Communication Unit to link two of the new Model 168s for a tightly coupled multiprocessing system of up to 16 megabytes of processor storage.
• High-speed buffer storage -- 8K was standard, 16K optional
• 7070/7074, 7080, and 709/7090/7094/7094 II compatibility features (these features mutually exclusive)
• A 1-usec CPU Timer and Clock Comparator
• 1-usec time-of-day clock
• Interval timer of 3.33-ms nominal resolution
• Byte boundary alignment
• Extended precision floating point
• A monitoring feature to trace user-defined program events
• Optional High-Speed Multiply feature Dual Channel I/O Bus to allow for dual cable paths and to increase the aggregate channel data rate
• Reliability, availability, serviceability features
• New instructions
• Support of System/7 for sensor-based applications via telecommunications