System/360 Model 195

IBM System/360 Model 195

IBM System/360 Model 195
Announced August 20, 1969 and
withdrawn February 9, 1977.

The following is the text of an IBM Data Processing Division press technical fact sheet distributed on August 20, 1969 and revised on September 19, 1969.

System/360 Model 195, announced today, is the most powerful computer in IBM's product line. It uses monolithic circuits, has a high-performance buffer memory and can perform many functions simultaneously.

The Model 195 has an internal processing speed about twice as fast as the Model 85, the next most powerful System/360. For example, in processing jobs with a large amount of floating point arithmetic - -such as matrix Eigenvalue calculations - - the Model 195 is 2.7 times faster internally than a Model 85 operating with a high-speed multiply feature.

Under Operating System/360 MVT (Multiprogramming with a Variable number of Tasks), the Model 195 can run most programs from other large models of System/360 without modification. In addition, most input/output devices used with other System/360 models also may be attached to the new computer.

Model 195 circuit technology

The Model 195 uses monolithic integrated circuits for the arithmetic and logic operations in the central processor, and as the storage medium in the 32,768-byte buffer memory.

As many as 664 transistors, diodes and other components - - the equivalent of about 64 complete circuits - - are placed on a single silicon memory chip less than one-eighth of an inch square. The monolithic circuits are so small that up to 53,000 components can fit in an area only one square inch.

Each memory chip can store 64 bits of data in binary form - -"zeros" and "ones." Two memory chips are mounted on a half-inch-square ceramic substrate similar to that used for IBM's Solid Logic Technology (SLT) microcircuits -- the basic technology for most System/360 models.

The monolithic circuits used in the Model 195's logic and arithmetic sections can transmit signals in three to five nanoseconds. Each chip contains from two to four circuits.

High-performance buffer storage

The monolithic memory circuits of the new computer's 32,768-byte buffer are a key factor in achieving the basic machine cycle of 54 nanoseconds.

The buffer is designed to keep pace with the central processing unit (CPU), which also has a 54-nanosecond cycle. This is 14 times faster than the main storage, which has a cycle time of 756 nanoseconds.

The buffer memory holds large blocks of data ready for use by the CPU and streams them into the central processor at the CPU's operating speed.

Each time the CPU needs data from main storage, it "asks" for at least one and up to eight bytes. Main storage, however, anticipates the CPU's future needs and always sends a block of 64 bytes. These 64-byte blocks are streamed into the buffer, which can accommodate up to 32,768 bytes in eight segments of 4,096 bytes each. Most of the time, the data next requested by the CPU will be located in adjacent memory blocks of the buffer.

In short, the CPU almost always will get data directly from the high-speed buffer rather than from main core memory.

The operation of the buffer memory is not apparent to the user. It works automatically without special programming. The user perceives only that the computer operates as if main storage were much faster than its nominal 756-nanosecond cycle speed.

Parallel operations in the Model 195

The Model 195 has five functionally separate units within its CPU: processor storage; storage bus control; instruction processor; fixed-point processor and floating-point processor. This internal organization allows the computer to overlap and process up to seven different operations at the same time.

The processor units operate concurrently and each may perform several operations simultaneously. For example, the floating-point processor can handle up to two additions and a multiplication at one time, markedly reducing the time required to execute instructions and process information.

Main core storage is organized into eight or 16 interleaved elements. The CPU can start a memory cycle with a different element every 54 nanoseconds, instead of waiting the full 756 nanoseconds. It seldom will get a "busy signal" from the memory and few, if any, machine cycles are wasted waiting for data because of this extremely high level of interleaving.

Configuration, price and availability

Main memory capacities available with the Model 195 are one-, two- and four-million bytes. The larger sizes allow users to solve complex problems more effectively and to run several programs at the same time under the control of Operating System/360 MVT (Multiprogramming with a Variable number of Tasks).

A typical Model 195 configuration might include a central processing unit with two-million byte core storage, an operator's console with a cathode-ray tube (CRT) display for diagnostics and operator control, three 2314 direct access storage facilities, two 2301 drum storage units, fourteen 2420 magnetic tape units, and several card read-punches and printers. A remote operator console also is available. Up to six selector channels and one multiplexer channel may be used with the Model 195.

Model 195 monthly system rental ranges from $165,000 to $275,000, with purchase prices from $7 million to $12.5 million, depending on configuration.

The Model 195 will be built at IBM's Poughkeepsie facilities. Initial delivery of the system will be scheduled for the first quarter of 1971.