| Model | Data Flow Width (bytes) | Cycle Time (nanoseconds) |
|---|---|---|
| 22 | 1 | 750 |
| 25 | 1 | 900 |
| 30 | 1 | 750 |
| 40 | 2 (1) | 625 |
| 44 | 4 | 250 |
| 50 | 4 | 500 |
| 65 | 8 | 200 |
| 67 | 8 | 200 |
| 75 | 8 | 195 |
| 85 | 8 | 80 |
| 91 | 8 | 60 |
| 95 | 8 | 60 |
| 195 | 8 | 54 |
(1) Certain registers and paths are 17 or 18 bits wide where a main storage address is processed in one cycle.
* Source: A. Pedegs, "System/360 And Beyond," IBM Journal Of Research And Development, Vol. 25, No. 5, September 1981, Table 1, p. 388.
| Model | Size(K Words) | Type | Cycle Time (nanoseconds) |
|---|---|---|---|
| 22 | 4 | RO | 750 |
| 25 | 8 | RW | 900 |
| 30 | 4 | RO | 750 |
| 40 | 4 | RO | 625 |
| 44 | none | ||
| 50 | 2.75 | RO | 500 |
| 65 | 2.75 | RO | 200 |
| 67 | 2.75 | RO | 200 |
| 75 | none | ||
| 85 | 2 | RO | 80 |
| 0.5 | RW | 80 | |
| 91 | none | ||
| 95 | none | ||
| 195 | none |
K = 1024
RO = Read-only
RW = Read-write (writable)
* Source: A. Pedegs, "System/360 And Beyond," IBM Journal Of Research And Development, Vol. 25, No. 5, September 1981, Table 1, p. 388.
| Model | Size (K bytes) | Bus Width (bytes) | Cycle Time** (nanoseconds) |
|---|---|---|---|
| 22 | 24-32 | 1 | 1500 |
| 25 | 16-48 | 2 | 900 |
| 30 | 16-64 | 1 | 1500 |
| 40 | 32-256 | 2 | 2500 |
| 44 | 32-256 | 4 | 1000 |
| 50 | 128-512 | 4 | 2000 |
| 1024-8192 | 4 x (1-2) | 8000 | |
| 65 | 256-1024 | 8 x 2 | 750 |
| 1024-8192 | 8 x (1-2) | 8000 | |
| 67 | 256-1024 | 8 x 2 | 750 |
| 75 | 256-1024 | 8 x (2-4) | 750 |
| 1024-8192 | 8 x (1-2) | 8000 | |
| 85 | 512-4096 | 16 x (2-4) | 960 |
| 91 | 2048-6144 | 8 x 16 | 780 |
| 95 | 1024 | 8 x 16 | 180 |
| 1024-6144 | 8 x 16 | 780 | |
| 195 | 1024-4096 | 8 x (8-16) | 756 |
K = 1024
* Source: A. Pedegs, "System/360 And Beyond," IBM Journal Of Research And Development, Vol. 25, No. 5, September 1981, Table 1, p. 388.
** Uses magnetic-core technology.