Detection error conditions

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An error is reported if the source program contains invalid instruction forms. Error occurs due to incompatibility between the POWER® family and PowerPC® architectures.

Error number 149 is reported if the source program contains instructions that are not supported in the intended target environment.

An error is reported if the source program contains invalid instruction forms. This error occurs due to incompatibilities between the POWER® family and PowerPC® architectures. Some restrictions that apply in the PowerPC® architecture do not apply in the POWER® family architecture. According to the PowerPC® architecture, the following invalid instruction forms are defined:
  • If an Rc bit, LK bit, or OE bit is defined as / (slash) but coded as 1, or is defined as 1 but coded as 0, the form is invalid. Normally, the assembler ensures that these bits contain correct values.

    Some fields are defined with more than one / (slash) (for example, "///"). If they are coded as nonzero, the form is invalid. If certain input operands are used for these fields, they must be checked. For this reason, the following instructions are checked:

    • For the PowerPC® System Call instructions or the POWER® family Supervisor Call instructions, if the POWER® family svca mnemonic is used when the assembly mode is PowerPC® type, the SV field must be 0. Otherwise, the instruction form is invalid and error number 165 is reported.
      Note: The svc and svcl instructions are not supported in PowerPC® target modes. The svcla instruction is supported only on the PowerPC® 601 RISC Microprocessor.
    • For the Move to Segment Register Indirect instruction, if the POWER® family mtsri mnemonic is used in PowerPC® target modes, the RA field must be 0. Otherwise, the instruction form is invalid and error number 154 is reported. If the PowerPC® mtsrin mnemonic is used in PowerPC® target modes, it requires only two input operands, so no check is needed.
  • For all of the Branch Conditional instructions (including Branch Conditional, Branch Conditional to Link Register, and Branch Conditional to Count Register), bits 0-3 of the BO field are checked. If the bits that are required to contain 0 contain a nonzero value, error 150 is reported.

    The encoding for the BO field is defined in the section "Branch Processor Instructions" of PowerPC® architecture. The following list gives brief descriptions of the possible values for this field:

    BO Description
    0000y Decrement the Count Register (CTR); then branch if the value of the decremented CTR is not equal to 0 and the condition is False.
    0001y Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is False.
    001zy Branch if the condition is False.
    0100y Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is True.
    0101y Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is True.
    011zy Branch if the condition is True.
    1z00y Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0.
    1z01y Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0.
    1z1zz Branch always.

    The z bit denotes a bit that must be 0. If the bit is not 0, the instruction form is invalid.
    Note: The y bit provides a hint about whether a conditional branch is likely to be taken. The value of this bit can be either 0 or 1. The default value is 0. The extended mnemonics for Branch Prediction as defined in PowerPC® architecture are used to set this bit to 0 or 1. (See Extended Mnemonics for Branch Prediction for more information.)

    Branch always instructions do not have a y bit in the BO field. Bit 4 of the BO field should contain 0. Otherwise, the instruction form is invalid.

    The third bit of the BO field is specified as the "decrement and test CTR" option. For Branch Conditional to Count Register instructions, the third bit of the BO field must not be 0. Otherwise, the instruction form is invalid and error 163 is reported.

  • For the update form of fixed-point load instructions, the PowerPC® architecture requires that the RA field not be equal to either 0 or the RT field value. Otherwise, the instruction form is invalid and error number 151 is reported.

    This restriction applies to the following instructions:

    • lbzu
    • lbzux
    • lhzu
    • lhsux
    • lhau
    • lhaux
    • lwzu (lu in POWER® family)
    • lwzux (lux in POWER® family)
  • For the update form of fixed-point store instructions and floating-point load and store instructions, the following instructions require only that the RA field not be equal to 0. Otherwise, the instruction form is invalid and error number 166 is reported.
    • lfsu
    • lfsux
    • lfdu
    • lfdux
    • stbu
    • stbux
    • sthu
    • sthux
    • stwu (stu in POWER® family)
    • stwux (stux in POWER® family)
    • stfsu
    • stfux
    • stfdu
    • stfdux
  • For multiple register load instructions, the PowerPC® architecture requires that the RA field and the RB field, if present in the instruction format, not be in the range of registers to be loaded. Also, RA=RT=0 is not allowed. If RA=RT=0, the instruction form is invalid and error 164 is reported. This restriction applies to the following instructions:
    • lmn (lm in POWER® family)
    • lswi (lsi in POWER® family)
    • lswx (lsx in POWER® family)
      Note: For the lswx instruction, the assembler only checks whether RA=RT=0, because the load register range is determined by the content of the XER register at run time.
  • For fixed-point compare instructions, the PowerPC® architecture requires that the L field be equal to 0. Otherwise, the instruction form is invalid and error number 154 is reported. This restriction applies to the following instructions:
    • cmp
    • cmpi
    • cmpli
    • cmpl
      Note: If the target mode is com, or ppc, the assembler checks the update form of fixed-point load instructions, update form of fixed-point store instructions, update form of floating-point load and store instructions, multiple-register load instructions, and fixed-point compare instructions, and reports any errors. If the target mode is any, pwr, pwr2, or 601, no check is performed.