Special-purpose register changes and special-purpose register field handling

Edit online

The special-purpose registers are defined in the POWER® family architecture.

TID, MQ, SDR0, RTCU, and RTCL are special-purpose registers (SPRs) defined in the POWER® family architecture. They are not valid in the PowerPC® architecture. However, MQ, RTCU, and RTCL are still available in the PowerPC® 601 RISC Microprocessor.

DBATL, DBATU, IBATL, IBATU, TBL, and TBU are SPRs defined in the PowerPC® architecture. They are not supported for the PowerPC® 601 RISC Microprocessor. The PowerPC® 601 RISC Microprocessor uses the BATL and BATU SPRs instead.

The assembler provides the extended mnemonics for "move to or from SPR" instructions. The extended mnemonics include all the SPRs defined in the POWER® family and PowerPC® architectures. An error is generated if an invalid extended mnemonic is used. The assembler does not support extended mnemonics for any of the following:

  • POWER2™-unique SPRs (IMR, DABR, DSAR, TSR, and ILCR)
  • PowerPC® 601 RISC Microprocessor-unique SPRs (HID0, HID1, HID2, HID5, PID, BATL, and BATU)
  • PowerPC 603 RISC Microprocessor-unique SPRs (DMISS, DCMP, HASH1, HASH2, IMISS, ICMP, RPA, HID0, and IABR)
  • PowerPC 604 RISC Microprocessor-unique SPRs (PIE, HID0, IABR, and DABR)

The assembler does not check the SPR field's encoding value for the mtspr and mfspr instructions, because the SPR encoding codes could be changed or reused. However, the assembler does check the SPR field's value range. If the target mode is pwr, pwr2, or com, the SPR field has a 5-bit length and a maximum value of 31. Otherwise, the SPR field has a 10-bit length and a maximum value of 1023.

To maintain source-code compatibility of the POWER® family and PowerPC® architectures, the assembler assumes that the low-order 5 bits and high-order 5 bits of the SPR number are reversed before they are used as the input operands to the mfspr or mtspr instruction.