Appendix D instructions common to POWER family, POWER2™, and PowerPC

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Instructions Common to POWER family, POWER2™, and PowerPC Instructions Common to POWER family, POWER2™, and PowerPC Instructions Common to POWER family, POWER2™, and PowerPC Instructions Common to POWER family, POWER2™, and PowerPC Instructions Common to POWER family, POWER2™, and PowerPC
Mnemonic Instruction Format Primary Op Code Extended Op Code
and[.] AND X 31 28
andc[.] AND with Complement X 31 60
b[l][a] Branch I 18  
bc[l][a] Branch Conditional B 16  
cmp Compare X 31 0
cmpi Compare Immediate D 11  
cmpl Compare Logical X 31 32
cmpli Compare Logical Immediate D 10  
crand Condition Register AND XL 19 257
crandc Condition Register AND with Complement XL 19 129
creqv Condition Register Equivalent XL 19 289
crnand Condition Register NAND XL 19 225
crnor Condition Register NOR XL 19 33
cror Condition Register OR XL 19 449
crorc Condition Register OR with Complement XL 19 417
crxor Condition Register XOR XL 19 193
eciwx External Control in Word Indexed X 31 310
ecowx External Control out Word Indexed X 31 438
eqv[.] Equivalent X 31 284
fabs[.] Floating Absolute Value X 63 264
fcmpo Floating Compare Ordered X 63 32
fcmpu Floating Compare Unordered XL 63 0
fmr[.] Floating Move Register X 63 72
fnabs[.] Floating Negative Absolute Value X 63 136
fneg[.] Floating Negate X 63 40
frsp[.] Floating Round to Single Precision X 63 12
lbz Load Byte and Zero D 34  
lbzu Load Byte and Zero with Update D 35  
lbzux Load Byte and Zero with Update Indexed X 31 119
lbzx Load Byte and Zero Indexed X 31 87
lfd Load Floating-Point Double D 50  
lfdu Load Floating-Point Double with Update D 51  
lfdux Load Floating-Point Double with Update Indexed X 31 631
lfdx Load Floating-Point Double Indexed X 31 599
lfs Load Floating-Point Single D 48  
lfsu Load Floating-Point Single with Update D 49  
lfsux Load Floating-Point Single with Update Indexed X 31 567
lfsx Load Floating-Point Single Indexed X 31 535
lha Load Half Algebraic D 42  
lhau Load Half Algebraic with Update D 43  
lhaux Load Half Algebraic with Update Indexed X 31 375
lhax Load Half Algebraic Indexed X 31 343
lhbrx Load Half Byte-Reversed Indexed X 31 790
lhz Load Half and Zero D 40  
lhzu Load Half and Zero with Update D 41  
lhzux Load Half and Zero with Update Indexed X 31 331
lhzx Load Half and Zero Indexed X 31 279
mcrf Move Condition Register Field XL 19 0
mcrfs Move to Condition Register from FPSCR X 63 64
mcrxr Move to Condition Register from XER X 31 512
mfcr Move from Condition Register X 31 19
mffs[.] Move from FPSCR X 63 583
mfmsr Move from Machine State Register X 31 83
mfspr Move from Special-Purpose Register X 31 339
mfsr Move from Segment Register X 31 595
mtcrf Move to Condition Register Fields XFX 31 144
mtfsb0[.] Move to FPSCR Bit 0 X 63 70
mtfsb1[.] Move to FPSCR Bit 1 X 63 38
mtfsf[.] Move to FPSCR Fields XFL 63 711
mtfsfi[.] Move to FPSCR Field Immediate X 63 134
mtmsr Move to Machine State Register X 31 146
mtspr Move to Special-Purpose Register X 31 467
mtsr Move to Segment Register X 31 210
nand[.] NAND X 31 476
neg[o][.] Negate XO 31 104
nor[.] NOR X 31 124
or[.] OR X 31 444
orc[.] OR with Complement X 31 412
rfi Return from Interrupt X 19 50
si Subtract Immediate D 12  
si. Subtract Immediate and Record D 13  
stb Store Byte D 38  
stbu Store Byte with Update D 39  
stbux Store Byte with Update Indexed X 31 247
stbx Store Byte Indexed X 31 215
stfd Store Floating-Point Double D 54  
stfdu Store Floating-Point Double with Update D 55  
stfdux Store Floating-Point Double with Update Indexed X 31 759
stfdx Store Floating-Point Double Indexed X 31 727
stfs Store Floating-Point Single D 52  
stfsu Store Floating-Point Single with Update D 53  
stfsux Store Floating-Point Single with Update Indexed X 31 695
stfsx Store Floating-Point Single Indexed X 31 663
sth Store Half D 44  
sthbrx Store Half Byte-Reverse Indexed X 31 918
sthu Store Half with Update D 45  
sthux Store Half with Update Indexed X 31 439
sthx Store Half Indexed X 31 407
xor[.] XOR X 31 316