PR/SM logical processor data section

This section contains a PR/SM logical processor data block. There is one for each logical processor in each configured partition. The terms logical processor and logical CPU refer to a logical core if multithreading is enabled for the reporting interval.

Offsets Name Length Format Description
0 0 SMF70PDT 8 binary Logical processor dispatch time, in microseconds. This is the number of microseconds that were accumulated during the measurement interval (during which a physical CPU was assigned to this logical CPU).

When associated with partition name PHYSICAL, this field contains the accumulated number of microseconds during which a physical CPU was busy, but the time could not be attributed to a specific logical partition. This time includes the time PR/SM was controlling the physical processor (LPAR management time), as well as any other time the processor was busy for any reason such as managing coupling facility traffic.
8 8 SMF70VPA 2 binary Logical processor address.
10 A SMF70BPS 2 binary Partition processor resource weight factor. If the value is X‘FFFF’, then the partition has been assigned dedicated processors.
12 C SMF70VPF 1 binary Logical processor flags
Bit
Meaning when set
0
Wait completion is enabled
1
Wait completion status has changed during interval
2
Weight has changed during interval
3
'Initial Capping' was set to 'ON' on the Hardware Management Console
4
'Initial Capping' status has changed during the interval
5
Logical processor varied online during the measurement interval
6
SMF70HW_Cap_Limit has changed during the interval
7
SMF70HWGr_Name or SMF70HWGr_Cap_Limit has changed during the interval.
13 D SMF70POF 1 binary Polarization flags
Bit
Meaning when set
0 - 1
Polarization indicator:
00
Horizontally polarized or polarization not indicated
01
Vertically polarized with low entitlement
10
Vertically polarized with medium entitlement
11
Vertically polarized with high entitlement
2
Polarization indication changed during interval
3-7
Reserved.
14 E SMF70CIX 2 binary Index to the CPU-identification name section that contains the EBCDIC name corresponding to the CPU type of the logical processor. This field is zero if there is no information available.
16 10 SMF70EDT 8 binary Logical processor effective dispatch time, in microseconds. The number of microseconds that were accumulated during the measurement interval (excluding LPAR management time), during which a physical CPU was assigned to this logical CPU.

When associated with partition name PHYSICAL, this field contains the accumulated number of microseconds during which a physical CPU was busy, but the time could not be attributed to a specific logical partition or to LPAR management of the physical processor. One example is time used for managing coupling facility traffic. This field is zero, if not supported by the hardware. LPAR management time is the time from SMF70PDT associated with partition name PHYSICAL minus the contents of this field.
24 18 SMF70ACS 4 binary Accumulated processor actual share.

To get the average processor actual share, this value has to be divided by the number of Diagnose samples (field SMF70DSA in the CPU control section).
28 1C SMF70MIS 2 binary Processor minimum share.
30 1E SMF70MAS 2 binary Processor maximum share.
32 20 SMF70NSI 4 binary Number of samples within 10% of the specified minimum.
36 24 SMF70NSA 4 binary Number of samples within 10% of the specified maximum.
40 28 SMF70ONT 8 binary Logical processor online time.
48 30 SMF70WST 8 binary Logical processor wait state time. SMF70WST is used only for internal purposes.
56 38 SMF70PMA 4 signed Average adjustment weight for pricing management. This value may be negative.
60 3C SMF70NSW 4 binary Number of diagnose samples where WLM considers to cap the set of logical CPUs of type SMF70CIX within the logical partition (see also SMF70NCA).
64 40 SMF70POW 4 binary Polarization weight for the logical CPU when HiperDispatch mode is active. See bit 2 of SMF70PFL. Multiplied by a factor of 4096 for more granularity. The value may be the same or different for all shared CPUs of type SMF70CIX. This is an accumulated value. Divide by the number of Diagnose samples SMF70DSA to get average weight value for the interval.
68 44 SMF70NCA 4 binary Number of diagnose samples where capping actually limited the usage of processor resources for the set of logical CPUs of type SMF70CIX within the logical partition.
72 48 SMF70HW_Cap_Limit 4 binary If not zero, absolute limit on partition usage of all CPUs of the type indicated in SMF70CIX in terms of a number specified in hundredths of a CPU. For example, a value of 250 indicates that the partition is limited to using 2.5 CPUs.
76 4C SMF70HWGr_Cap_Limit 4 binary If not zero, absolute limit on partition usage of all CPUs of the type indicated in SMF70CIX that are members of the same hardware group, in terms of a number specified in hundredths of a CPU. For example, a value of 250 indicates that the hardware group is limited to using 2.5 CPUs.
80 50 SMF70MTIT 8 binary Multithreading Idle Time in microseconds accumulated for all threads of a dispatched core. This field is only valid if SMF70MTID is not zero for this partition.
88 58 SMF70LPF 1 binary Additional processor flags.
Bit
Meaning when set
0
Topology has changed during this interval.
1 - 7
Reserved.
Fields SMF70MaxNL and SMF70CordL1 - SMF70CordL6 contain CPU topology location information for logical and physical core homes. This information is available with SMF record level SMF70SRL > X'8E'(142).
89 59 SMF70MaxNL 1 binary Maximum number of topology nesting levels. The value is model dependent with a maximum of 6.
Value
Meaning
0
The model does not provide information about the topological nesting levels.
1
There is no actual topological nesting structure.
2 - 6
Topological nesting levels are available, beginning with field SMF70CordL1 up to field SMF70CordLx, where x is the value that defines the maximum number of topology nesting levels.
90 5A SMF70CordL1 1 binary Coordinate of the preferred dispatch location of the logical core at topological nesting level 1. Valid if SMF70MaxNL > 0.
91 5B SMF70CordL2 1 binary Coordinate of the preferred dispatch location of the logical core at topological nesting level 2. Valid if SMF70MaxNL > 1.
92 5C SMF70CordL3 1 binary Coordinate of the preferred dispatch location of the logical core at topological nesting level 3. Valid if SMF70MaxNL > 2
93 5D SMF70CordL4 1 binary Coordinate of the preferred dispatch location of the logical core at topological nesting level 4. Valid if SMF70MaxNL > 3
94 5E SMF70CordL5 1 binary Coordinate of the preferred dispatch location of the logical core at topological nesting level 5. Valid if SMF70MaxNL > 4
95 5F SMF70CordL6 1 binary Coordinate of the preferred dispatch location of the logical core at topological nesting level 6. Valid if SMF70MaxNL > 5
96 60 * 8   Reserved.