System/370 I/O Instructions
The following System/370 I/O instructions are provided when 370
Accommodation is active:
- START I/O (SIO)
- START I/O FAST RELEASE (SIOF)
- TEST I/O (TIO)
- HALT I/O (HIO)
- HALT DEVICE (HDV)
- CLEAR I/O (CLRIO)
- DIAGNOSE code X'18'
- DIAGNOSE code X'20'
- DIAGNOSE code X'98', SIOF-Real subcode
These instructions operate the same under 370 Accommodation as
they do for System/370, with the following changes:
- The operand System/370 I/O address is treated as an ESA-family device number.
- The addressed channel and device is available to all CPUs in the configuration. The instructions are not restricted to a single CPU as they would be in a 370 virtual machine on VM/ESA.
- The I/O address specified is not limited to X'1FFF', which is normally the case for a 370 virtual machine on VM/ESA. This has the effect of making it appear as though there are 256 channels available to the program.
- If vestigial status is pending at the subchannel, it is discarded before proceeding with instruction execution. For more information on this new type of status in the subchannel, see Vestigial Status.
- If the subchannel is not enabled at the beginning of instruction execution, it becomes enabled before proceeding with instruction execution. That is, bit 8 of word 1 of the subchannel-information block associated with the subchannel is set to one.
- I/O interruptions generated from operations initiated by these instructions are masked by interruption subclass (ISC) not channel number. Whether a CPU is enabled for interruptions is determined, therefore, by bit 6 of the PSW and the interruption-subclass mask in control register 6, not channel-enablement bits in the PSW and control register 2.
For the START I/O FAST RELEASE (SIOF) and CLEAR I/O (CLRIO) instructions, it should additionally be noted that bit 0 of control register 0, the block-multiplexing-control bit, is examined during instruction execution, even though that bit position is unassigned in the ESA-family architectures.