TRACE: Command Responses

Purpose

In this section are illustrated the command responses for each of the TRACE command operands. These response descriptions use the following symbols:

aaaaaaaa

aaaaaaaaaaaaaaaa

aaaaaaaa_aaaaaaaa

A storage address, followed by a single quotation mark (’) if a primary address space storage address or a double quotation mark (”) if a home address space storage address.

For external and I/O interruptions, it is the instruction address at the point of interruption, taken from the corresponding old PSW.

For program interruptions, it is the address of the instruction that encountered the program interruption. More specifically:

For a PER event (either alone or accompanied by some other program interruption condition), it is the PER event address.
For a nullifying program interruption not accompanied by a PER event, it is the instruction address in the program old PSW.
For a suppressing, terminating, or completing program interruption not accompanied by a PER event, it is the instruction address in the program old PSW, minus the instruction length code.^¹

When a program interruption occurs during transactional-execution mode, two addresses are generally reported. First, the instruction at the point of the transaction abort is shown. Then, on the program-interruption (PROG) line, the address at left shows the address of the TBEGIN or TBEGINC instruction of the outermost aborted transaction. In some cases, the location of the abort is not known; the instruction display line is then omitted, and the PROG line shows the instruction address from the program old PSW. This is either the address after the TBEGIN or the address of the TBEGINC.

Start of change It is model-dependent whether transactional-execution mode is entered. For more information, see z/VM support for the IBM z17 family in the z/VM: Migration Guide. End of change

tttttttt

tttttttt_tttttttt

tttttttttttttttt

A transfer address, followed by a single quotation mark (’) if DAT.^²

xxxxxxxx

An instruction, CSW status, and other such items.

gggggggg

A second-level channel command word, CSW status, and other guest output.

hhhhhhhh

A first-level channel command word, CSW status, and other such host output.

oooo

A first-level CCW offset.

address1

The address of operand 1 (for SI and SS formats only).^²

address2

The address of operand 2 (for RX, RS, S, and SS formats only).^²

The operands address1 and address2 may be question marks if:

the address cannot be resolved because the base or index registers used to compute them have been altered by the instruction
the operand is ignored by the instruction.

address3/address4/address5

Addresses of storage alterations.^²

content1

The contents of the R1 field (RRE format only).^¹

content2

The contents of the R2 field (RRE format only).^¹

vvvv

A virtual device number.

vsch

A virtual subchannel number.

mnem

The mnemonic for an instruction. This is a 7-character field in which the mnemonic is left-justified.

code

An interruption code number in hexadecimal.

name

An interruption name (for example, OPERATION, ADDRESSING) which may be combined with TRANSACTION ABORT, PER or PROGRAM EVENT RECORDER.

CC n

The condition code number (0, 1, 2, or 3).

Note: The condition code will not always be displayed.

Gnn

A general register with altered contents.

cccccccc

cccccccccccccccc

cccccccc_cccccccc

The address generated and loaded by a LOAD ADDRESS or LOAD ADDRESS EXTENDED instruction.^²

ss

A status byte.

FSA=nnnnnnnn

FSA=nnnnnnnnnnnnnnnn

FSA=nnnnnnnn_nnnnnnnn

The failing storage address if valid. If it is not valid, nothing is shown.^²

zz

An altered byte of an EXECUTE instruction, formed by inclusive-ORing the low byte of R1 with the second byte of the executed instruction.

***

A prefix indicating virtual machine interruption.

*TN

A prefix indicating a virtual machine program interruption occurred during transactional execution mode. The address that follows is the start of the aborted transaction when the instruction at the point of the abort is also displayed in the preceding line. When the abort point cannot be determined, the interrupting instruction is not shown, and the address that follows *TN is the instruction address from the program old PSW. This is either the address after the TBEGIN or the address of the TBEGINC.

Start of change It is model-dependent whether transactional-execution mode is entered. For more information, see z/VM support for the IBM z17 family in the z/VM: Migration Guide. End of change

->

As a prefix indicating transfer of control, this symbol is present at the beginning of a line whenever the displayed instruction does not immediately follow the last instruction displayed. As a suffix for a successful branch instruction, it precedes the address being transferred to.

-

A suffix used on storage operand addresses to indicate that the address being displayed is one byte past the end of the storage altered by the instruction.

>>

An indication of storage alteration, followed by the operand address.

=

A prefix used with LOAD ADDRESS or LOAD ADDRESS EXTENDED to show that the actual data is shown rather than computing the operand address by base and displacement.

ARareg

An access register with altered contents.

SPACEowner:space_name

identifies the owner’s user ID and the name of the address space in which the trace event occurred. It is displayed only for XC virtual machines.

ASITasit

identifies the address space identification token of the address space in which the trace event occurred. It is displayed only for XC virtual machines.

Basic Instruction Display (when full trace support is provided)

aaaaaaaa mnem xxxxxxxx address1 address2 CC n
aaaaaaaa_aaaaaaaa mnem xxxxxxxx address1
                                address2 CC n

Basic Instruction Display (when full trace support is not provided)

aaaaaaaa mnem xxxxxxxx                   CC n

Executed Instructions

Note: If the target of an EXECUTE instruction modifies a register that was also used to address the target instruction, that is, base or index registers, trace output starting with address1 and continuing to the end of the trace entry will be incorrect.

aaaaaaaa EX xxxxxxxx address1 mnem xxzzxxxx address1 address2 CC n
aaaaaaaa_aaaaaaaa EX xxxxxxxx
      address1 mnem xxzzxxxx address1 address2 CC n

Load Address and Load Address Extended (LA or LAE) Instructions

aaaaaaaa mnem xxxxxxxx = cccccccc CC n
aaaaaaaa_aaaaaaaa mnem xxxxxxxx = cccccccc CC n

RRE Format Instructions using General Registers

aaaaaaaa mnem xxxxxxxx content1 content2 CC n
aaaaaaaa_aaaaaaaa mnem xxxxxxxx content1
                                content2 CC n

RRE Format Instructions using Floating Point Registers

aaaaaaaa mnem xxxxxxxx CC n

Perform-Locked-Operation Instructions


aaaaaaaa PLO xxxxxxxx >> address1 address2
                   [address3 address4 address5] CC n
aaaaaaaa_aaaaaaaa PLO xxxxxxxx >> address1 
                   address2 [address3 address4]
       [address5] CC n

RI Format Instructions

aaaaaaaa mnem xxxxxxxx CC n

Instructions Altering Storage

aaaaaaaa mnem xxxxxxxx >> address1 address2 CC n

Successful Branch Instructions (including SVC and LPSW)

aaaaaaaa mnem xxxxxxxx -> tttttttt CC n

Instructions Satisfying GPR Alteration Tracing

aaaaaaaa mnem xxxxxxxx address1 address2
 CC n Gnn=xxxxxxxx
    Gnn=xxxxxxxx    Gnn=xxxxxxxx    Gnn=xxxxxxxx    …

aaaaaaaa_aaaaaaaa mnem xxxxxxxx address1 address2
 CC n Gnn=xxxxxxxx_xxxxxxxx
    Gnn=xxxxxxxx_xxxxxxxx    Gnn=xxxxxxxx_xxxxxxxx    Gnn=xxxxxxxx_xxxxxxxx

Instructions Satisfying Access Register Alteration Tracing

aaaaaaaa mnem xxxxxxxx address1 address2
CC n ARareg=xxxxxxxx
    ARareg=xxxxxxxx    ARareg=xxxxxxxx    ARareg=xxxxxxxx    …

aaaaaaaa_aaaaaaaa mnem xxxxxxxx address1 address2
CC n ARareg=xxxxxxxx
    ARareg=xxxxxxxx    ARareg=xxxxxxxx    ARareg=xxxxxxxx    …

External Interruptions

*** aaaaaaaa EXT  code -> tttttttt

Program Interruptions

(Instruction displayed where possible)

*** aaaaaaaa PROG code -> tttttttt name

Transactions Aborted by Program Interruptions

(Instruction displayed where possible)

*TN aaaaaaaaaaaaaaaa PROG code -> tttttttttttttttt

Adapter Interruption Facility Interruptions

***  aaaaaaaa     ADAPTER INT   ->    tttttttt   ISC x     SCH TYPE y

where:

aaaaaaaa = I/O Old PSW (where your program was interrupted)
tttttttt = I/O New PSW (the I/O interruption handler)
ISC x = the Interruption Subclass (bits 2–4 of the
Host Interruption Identification Word)
SCH TYPE y = the Subchannel Type (bits 17–19 of the
Host Interruption Identification Word)

Virtual Machine Check Interruptions

(Instruction displayed where possible)

*** aaaaaaaa
MCH -> tttttttt type type …
             (FSA=nnnnnnnn)

aaaaaaaa

identifies the address contained in the second word of the old PSW, if valid, of the machine check. If the PSW instruction address is marked not valid, question marks appear in place of the address.

tttttttt

identifies the address contained in the second word of the new PSW for the machine check.

type

identifies one or more of the machine check codes found in z/Architecture Principles of Operation. The major virtual machine check codes are:

FSA=nnnnnnnn

identifies the FAILING STORAGE ADDRESS if valid. If it is not valid, nothing is shown.

Table 1. Machine Check Codes
Number	Code	Machine Check
0	SD	System damage
1	PD	Instruction processing damage
2	SR	System recovery
3	TD	Interval timer damage
4	CD	Timing facility damage
5	ED	External damage
6	Unused
7	DG	Degradation
8	W	Warning
9	CP	Channel report pending
10	SP	Service processor damage
11	CK	Channel subsystem damage
12	Unused
13	Unused
14	B	Backed up

I/O interruptions

*** aaaaaaaa
I/O vvvv -> tttttttt
SCH vsch PARM xxxxxxxx

I/O instructions

aaaaaaaa SSCH xxxxxxxx address2
CC 0 SCH vsch DEV vvvv
    CPA xxxxxxxx PARM xxxxxxxx
    KEY x FPI xx LPM xx

SSCH instructions for Transport Mode I/O may also include the following data structures, if valid:

     TCW +ooooo xxxxxxxx xxxxxxxx ...
    TCCB +ooooo xxxxxxxx xxxxxxxx ...
     TSB +ooooo xxxxxxxx xxxxxxxx ...
   TIDAW        xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
    DATA +ooooo xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx

CPA: identifies the channel program address specifying the absolute address of the first channel command word to be processed on the device.
PARM: identifies the interruption parameter to be returned with any interruption for the specified channel command words.
KEY: identifies the storage protection key to be used.
FPI: identifies the format, prefetch, initial status control byte.
LPM: identifies the logical path mask.
TCW: the Transport Command Word (Transport Mode only).
TCCB: the Transport Command Control Block (Transport Mode only).
TSB: the Transport Status Block (Transport Mode only).
TIDAW: the Transport Indirect Data Address Word (Transport Mode only).
DATA: the data associated with a TIDAW (Transport Mode only).

aaaaaaaa TSCH xxxxxxxx address2 CC 0 SCH vsch DEV vvvv
    CCWA xxxxxxxx DEV STS xx SCH STS xx CNT xxxx
    KEY x FPI xx CC x CTLS xxxx
    SENSE DATA:    xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
                   xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx

aaaaaaaa TSCH xxxxxxxx address2 CC 1 SCH vsch DEV vvvv
    KEY x FPI xx CC x CTLS xxxx

CCWA: identifies the ending channel command word address when I/O is completed.
DEV STS: identifies the unit status for the device.
SCH STS: identifies the channel status for the subchannel.
CNT: identifies the residual CCW count upon I/O completion.
KEY: identifies the key used for storage protection.
FPI: identifies the format, prefetch, initial status control byte used. It also indicates a no path available condition and a confirmed I/O condition code 0.
CC x: identifies the condition code for the requested I/O operation.
CTLS: identifies the function and activity control bytes.
SENSE DATA: identifies optional concurrent sense data when concurrent sense is enabled and a unit check has occurred.

aaaaaaaa TPI xxxxxxxx address2 CC 1
    SCH xxxx DEV xxxx PARM xxxxxxxx

SCH: identifies the subchannel requesting the interruption.
DEV: identifies the subchannel device.
PARM: identifies the interruption parameter supplied by the virtual machine; it is zero if the interruption is unsolicited.

Instructions/Condition Codes

aaaaaaaa mnem xxxxxxxx address2
CC n SCH vsch DEV vvvv

Executed I/O Instructions

aaaaaaaa EX xxxxxxxx aaaaaaaa mnem xxzzxxxx address2
CC n
    SCH vsch DEV vvvv

(followed by fields as before.)

CCW Tracing Display Formats

Define Extent CCWs for Mini-DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh ........
 EXTENT                 hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh

Define Extent CCWs for Attached DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh hhhhhhhh
 EXTENT                 hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh

Locate CCWs for Mini-DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh ........
 LOCATE         gggggggg gggggggg         hhhhhhhh hhhhhhhh

Locate CCWs for Attached DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh hhhhhhhh
 LOCATE         gggggggg gggggggg         hhhhhhhh hhhhhhhh

Locate Record CCWs for Mini-DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh ........
 LOCATE RECORD          hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh

Locate Record CCWs for Attached DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh hhhhhhhh
 LOCATE RECORD          hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh

Prefix CCWs for Mini-DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh ........
 PX  hhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhh

CCW parameter bytes displayed are: 0–1, 3, 12–27, 44–56

Prefix CCWs for Attached DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh hhhhhhhh
 PX  hhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh hhhhhhhhhhhhhhhhhhhhhhhhhh

CCW parameter bytes displayed are: 0–1, 3, 12–27, 44–56

Search CCWs for Mini-DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh ........
 SEARCH         gggggggg gg               hhhhhhhh hh

Search CCWs for Attached DASDs

CCW    aaaaaaaa
gggggggg gggggggg   oooo  hhhhhhhh hhhhhhhh
 SEARCH         gggggggg gg               hhhhhhhh hh

Seek CCWs for Mini-DASDs

CCW    aaaaaaaa gggggggg gggggggg   oooo  hhhhhhhh ........
 SEEK           gggggggg gggg             hhhhhhhh hhhh

Seek CCWs for Attached DASDs

CCW    aaaaaaaa
gggggggg gggggggg   oooo  hhhhhhhh hhhhhhhh
 SEEK           gggggggg gggg             hhhhhhhh hhhh

SEEK CCWs with a Virtual Channel Simulator

VDEV vvvv  CCW  gggggggg gggggggg STS ss DATA gggggggggggg STS ss
CCW                                    oooo  hhhhhhhh ........
 SEEK                                        hhhhhhhh hhhh

CCWs with a Virtual Channel Simulator

VDEV vvvv  CCW  gggggggg gggggggg STS ss DATA hhhhhhhhhhhhhhhh … STS ss

Seek CCW — Set File Mask CCW Sequence with a Virtual Channel Simulator

VDEV vvvv  CCW  gggggggg gggggggg STS ss ss DATA STS ss
           CCW  gggggggg gggggggg STS ss DATA gg STS ss

Seek CCW — Set File Mask CCW Sequence with a Real Channel

CCW                                  oooo  hhhhhhhh ........
 SEEK                                      hhhhhhhh hhhhhhhh
CCW                                  oooo  hhhhhhhh ........
                                           hh

TIC CCWs

CCW    aaaaaaaa  gggggggg gggggggg
  oooo  hh00oooo hhhhhhhh

TIC CCWs with Virtual Channel Simulator

CCW    gggggggg gggggggg   TIC   aaaaaaaa

Other CCWs

CCW    aaaaaaaa  gggggggg gggggggg
  oooo  hhhhhhhh hhhhhhhh

CCWs with Data Crossing Page Boundaries

CCW    aaaaaaaa  gggggggg gggggggg   oooo  hhhhhhhh ........
 IDAL                                      hhhhhhhh
 IDAL                                      hhhhhhhh

… as many IDALs as needed …

CCWs with User IDALs

CCW    aaaaaaaa  gggggggg gggggggg   oooo  hhhhhhhh ........
 IDAL            gggggggg                  hhhhhhhh
 IDAL            gggggggg                  hhhhhhhh
 …             …                       …

CCWs with User Format-2 IDALs

CCW              aaaaaaaa  gggggggg gggggggg   oooo  hhhhhhhh ........
 IDAL             gggggggg_gggggggg         hhhhhhhh_hhhhhhhh  
 IDAL             gggggggg_gggggggg         hhhhhhhh_hhhhhhhh  
 …             …                       …

CCWs with Virtual Channel IDAWs

CCW
 IDAW  gggggggg  DATA  gggg

CCWs with Virtual Channel Format-2 IDAWs

CCW
 IDAW  gggggggg_gggggggg  DATA  gggggggg

Data Transfer over Eight Bytes with Virtual Channel Simulator

CCW                                        hhhhhhhh hhhhhhhh
                                           hhhhhhhh hhhh

Suspend with Virtual Channel Simulator

CCW    gggggggg gggggggg ***SUSPENSION***

CCWs with Virtual Channel MIDAWs (Fully Simulated CCWs)

CCW
 MIDAW  gggggggg_gggggggg  DATA  gggggggg

CCWs with User MIDAL (CCWs Sent to Hardware)

CCW     aaaaaaaa  gggggggg gggggggg   oooo  hhhhhhhh ........
 MIDAW   gggggggg_gggggggg         gggggggg_gggggggg
         hhhhhhhh_hhhhhhhh         hhhhhhhh_hhhhhhhh
 MIDAW   gggggggg_gggggggg         gggggggg_gggggggg
         hhhhhhhh_hhhhhhhh         hhhhhhhh_hhhhhhhh
 …     …                       …

¹ The number of hexadecimal digits displayed depends on the virtual machine mode: eight for ESA/390-mode and ESA/XC-mode machines; 16 for z/Architecture®-mode and z/XC-mode machines. If SET UNDERSCORE is set on, the 16 digits are separated in the middle with an underscore for easier readability.

² The number of hexadecimal digits displayed depends on the guest addressing mode: eight for 24-bit or 31-bit addressing mode; 16 for 64-bit addressing mode.