Interrupt processing

The interrupt mechanism is the means for coordinating multiprogramming between an I-stream engine and the engines of a channel subsystem. An interrupt is a hardware enforced transfer of control within an I-stream engine. An interruption usually takes place after an instruction is completed and before interpretation of the next instruction is started. The logic built into z/Architecture support is enough to preserve the information necessary to return to the interrupted point of departure. Further, interrupts of the same kind are inhibited generally by the z/TPF system, at least long enough to preserve the state of the I-stream engine and to save control information and data. Ultimately, return is made to the interrupted code without loss of data. Classes of interrupts inhibited in an I-stream engine do not prevent interrupt generating signals to be set in the device controllers and devices. These signals are essentially stacked within the channel subsystem, which presents the signals to any I-stream engine that is willing to accept the interruption.

A program status word (PSW) includes the instruction address and other information used to control instruction sequencing and to determine the state of the I-stream engine. A PSW also includes the bits used to inhibit or permit interrupts. In addition to the current PSW, which is the PSW in control of an I-stream engine, there are PSWs associated with each class of interrupts. There are six classes of interrupts possible:
  • External
  • Machine check
  • I/O
  • Program
  • Restart
  • Supervisor call (SVC).

Each class of interrupts is assigned an old and a new PSW. The old and new PSWs are held in the prefix area for the I-stream engine.

When an interrupt occurs, the current PSW is stored into the old PSW for the class of interrupt, and the new PSW for the class of interrupt is loaded into the current PSW.