External time reference synchronization check

External time reference (ETR) hardware features determine the relationships between clocks.

Control register 0 contains a bit that determines whether the clock on that processor is sensitive to the timing pulses sent to it. Control register 0 also contains a bit that determines whether synchronization checks (sync checks) are recognized. If this bit is set, sync checks are recognized. Recognizing a sync check means that when the remote clock reaches the one second mark the remote clock expects a synchronization pulse to be sent by the in-use clock and, if this pulse does not occur at that moment, an external interrupt takes place on the remote processor. A sync check is a catastrophic condition under most configurations.

When a sync check occurs, the external interrupt handler runs to determine which error occurred. When the sync check is isolated, TOD clock synchronization routines are called to attempt to resolve the error. If the processor in error is a remote processor in a loosely coupled complex with an ETR (such as the Sysplex Timer), the system attempts to revalidate the hardware. If the hardware is operational, the processor is not taken down. All other scenarios are catastrophic. After a catastrophic sync check, the system reloads, and the time must be confirmed with an external source. If a sync check is not catastrophic, the CPC changes to local timing mode in the loosely coupled complex. To restore the CPC to the synchronization of the complex, reset the time on the owning processor, or IPL the CPC.