Macro examples

For example, if you are using c89, you might have a makefile with these definitions:

USER = /usr/jsmith
# directory where object modules are kept
DIROBJ = $(USER)/project/obj
# directory where src modules are kept
DIRSRC = $(USER)/project/src
$(DIROBJ)/module.o : $(DIRSRC)/module.c
   # compile the file
   $(CC) -c $(DIRSRC)/module.c
   # and move the object file to the specified directory
   mv $(DIRSRC)/module.o $(DIROBJ)/module.o

This makefile defines macros for the directories that contain source files and object modules. These macros can be changed easily. For example, if you want to store all the object files in a different directory, just change the definition of DIROBJ.

The next example comes from a difference between various C compilers. Some compilers put compiled object code into files ending with .obj and executable code into files ending with .exe, whereas others put the object code into files ending with .o and executable code into files with no suffix. If you plan to switch from one system to another, you might use the following macro definitions:

O = .obj
E = .exe
program$(E) : module1$(O) module2$(O) …
    recipe
module1$(O) : …

If you change to a compiler that uses the .o suffix for object files, you can just change the definition of O to change all the suffixes in the file. Similarly, if you change to a system that does not use suffixes with executable programs, you can define:

E =

so that $(E) expands to an empty (null) string.

When a macro name consists of a single character, make lets you omit the parentheses, so that, for example, you can write the macro $(E) as $E. You will find this useful if you use common suffix macros:

program$E : module1$O module2$O …
    recipe
module1$O : …