| 0 |
(0) |
STRUCTURE |
0 |
FLCESAME |
FLCE 0x: defined by architecture |
| 0 |
(0) |
CHARACTER |
8 |
FLCEIPPSW |
FLCE 0x: IPL PSW |
| 8 |
(8) |
CHARACTER |
8 |
FLCEICCW1 |
FLCE 8x: IPL CCW1 |
| 16 |
(10) |
CHARACTER |
8 |
FLCEICCW2 |
FLCE 10x: IPL CCW1 |
| 24 |
(18) |
CHARACTER |
104 |
FLCER018 |
FLCE 18x: reserved |
| 128 |
(80) |
CHARACTER |
4 |
FLCEEPARM |
FLCE 80x: External interruption parameter |
| 132 |
(84) |
CHARACTER |
2 |
FLCECPUAD |
FLCE 84x: CPU address |
| 134 |
(86) |
CHARACTER |
2 |
FLCEEICODE |
FLCE 86x: External interruption code |
| 136 |
(88) |
CHARACTER |
4 |
FLCESDATA |
FLCE 88x: Additional SVC interruption data |
| 136 |
(88) |
CHARACTER |
2 |
FLCESDATABYTE0 |
FLCE 88x: |
| 136 |
(88) |
CHARACTER |
1 |
|
FLCE 88x: Reserved |
| 137 |
(89) |
BITSTRING |
1 |
FLCESILC |
FLCE 89x: SVC interruption length code |
Bit definitions:
|
| |
|
.... .111 |
FLCESILCB |
"X'07'" FLCE 89x: Significant bits in ILC. Last bit is
always zero |
| 138 |
(8A) |
CHARACTER |
2 |
FLCESICODE |
FLCE 8Ax: SVC interruption code |
| 140 |
(8C) |
CHARACTER |
4 |
FLCEPDATA |
FLCE 8Cx: Additional Program interruption data |
| 140 |
(8C) |
CHARACTER |
2 |
FLCEPDATABYTE0 |
FLCE 8Cx: |
| 140 |
(8C) |
CHARACTER |
1 |
|
FLCE 8Cx: Reserved |
| 141 |
(8D) |
BITSTRING |
1 |
FLCEPILC |
FLCE 8Dx: Program interruption length code |
Bit definitions:
|
| |
|
.... .111 |
FLCEPILCB |
"X'07'" FLCE 8Dx: Significant bits in ILC. Last bit is
always zero |
| 142 |
(8E) |
CHARACTER |
2 |
FLCEPICODE |
FLCE 8Ex: Program interruption code |
| 142 |
(8E) |
BITSTRING |
1 |
FLCEPICODE0 |
FLCE 8Ex: Exception extension code |
| 143 |
(8F) |
BITSTRING |
1 |
FLCEPICODE1 |
FLCE 8Fx: 8-bit interruption code |
Bit definitions:
|
| |
|
1... .... |
FLCEPIPER |
"X'80'" FLCE 8Fx: PER interruption code |
| |
|
.1.. .... |
FLCEPIMC |
"X'40'" FLCE 8Fx: Monitor Call interruption code |
| |
|
..11 1111 |
FLCEPIPC |
"X'3F'" FLCE 8Fx: An unsolicited program interruption
has occurred if any of these bits are on |
| 144 |
(90) |
CHARACTER |
4 |
FLCEPIINFORMATION |
FLCE 90x: |
| 144 |
(90) |
CHARACTER |
3 |
|
|
| 147 |
(93) |
BITSTRING |
1 |
FLCEDXC |
FLCE 93x: Data exception code for PI 7 |
| 147 |
(93) |
BITSTRING |
1 |
FLCEVXC |
FLCE 93x: Vector exception code for PI 1B |
| 148 |
(94) |
CHARACTER |
2 |
FLCEMCNUM |
FLCE 94x: Monitor class number |
| 150 |
(96) |
CHARACTER |
2 |
FLCEPERCODE |
FLCE 96x: PER code |
| 150 |
(96) |
BITSTRING |
1 |
FLCEPERCODE0 |
FLCE 96x: Byte 0 |
Bit definitions:
|
| |
|
1... .... |
FLCEPERSB |
"X'80'" FLCE 96x: PER successful branch event |
| |
|
.1.. .... |
FLCEPERIF |
"X'40'" FLCE 96x: PER instruction fetch event |
| |
|
..1. .... |
FLCEPERSA |
"X'20'" FLCE 96x: PER storage alteration event |
| |
|
.... 1... |
FLCEPERSAR |
"X'08'" FLCE 96x: PER storage alteration using real event |
| |
|
.... .1.. |
FLCEPERZAD |
"X'04'" FLCE 96x: PER zero address detection |
| |
|
.... ..1. |
FLCEPERTRANSACTIONEND |
"X'02'" |
| 151 |
(97) |
BITSTRING |
1 |
FLCEPERATMID |
FLCE 97x: PER addressing and translation mode ID |
Bit definitions:
|
| |
|
1... .... |
FLCEPERPSW4 |
"X'80'" FLCE 97x: PER PSW bit 4 |
| |
|
.1.. .... |
FLCEPERATMIDVALID |
"X'40'" FLCE 97x: When 1, the ATMID bits are valid |
| |
|
..1. .... |
FLCEPERPSW32 |
"X'20'" FLCE 97x: PER PSW bit 32 |
| |
|
...1 .... |
FLCEPERPSW5 |
"X'10'" FLCE 97x: PER PSW bit 5 |
| |
|
.... 1... |
FLCEPERPSW16 |
"X'08'" FLCE 97x: PER PSW bit 16 |
| |
|
.... .1.. |
FLCEPERPSW17 |
"X'04'" FLCE 97x: PER PSW bit 17 |
| |
|
.... ..11 |
FLCEPERASCEID |
"X'03'" FLCE 97x: PER ASCE identification. If a storage
alteration event when DAT is on, identifies the ASCE used: '00' -
primary ASCE '01' - AR-specified AR. '10' - secondary ASCE '11' -
home ASCE |
| 152 |
(98) |
CHARACTER |
8 |
FLCEPER |
FLCE 98x: PER address |
| 152 |
(98) |
CHARACTER |
4 |
FLCEPERW0 |
FLCE 98x: PER address word 0 |
| 156 |
(9C) |
ADDRESS |
4 |
FLCEPERW1 |
FLCE 9Cx: PER address word 1 |
| 160 |
(A0) |
BITSTRING |
1 |
FLCEEAID |
FLCE A0x: Exception access ID (The AR number involved
in the translation exception when bits 30-31 of the TEA='01'). On
a PIC 2C when ALRF is installed, additional bits are set |
Bit definitions:
|
| |
|
1... .... |
FLCEEAID0 |
"X'80'" Bit 0 of EAID. Zero |
| |
|
.1.. .... |
FLCEEAID1 |
"X'40'" Bit 1 of EAID. Zero |
| |
|
..1. .... |
FLCEEAID2 |
"X'20'" Bit 2 of EAID. Set only when PIC 2C for PTI or
for PASN translation on PR |
| |
|
...1 .... |
FLCEEAID3 |
"X'10'" Bit 3 of EAID. Set only when PIC 2C for SSAIR
or for SASN translation on PR |
| |
|
.... 1111 |
FLCEEAID_ARNUM |
"X'0F'" AR number. Zero when Bit 1 or Bit 2 is set |
| 161 |
(A1) |
BITSTRING |
1 |
FLCEPERAID |
FLCE A1x: PER access ID (the access register number involved
in the PER storage alteration event) |
| 162 |
(A2) |
BITSTRING |
1 |
FLCEOPACID |
FLCE A2x: |
| 163 |
(A3) |
CHARACTER |
1 |
FLCEAMDID |
FLCE A3x: Architecture mode ID (See FLCARCH in IHAPSA) |
Bit definitions:
|
| |
|
.... ...1 |
FLCELOEME |
"X'01'" Logout is Z/Architecture |
| 164 |
(A4) |
ADDRESS |
4 |
FLCEMPL |
FLCE A4x: MPL address |
| 168 |
(A8) |
CHARACTER |
8 |
FLCETEID |
FLCE A8x: Translation exception identification |
| 168 |
(A8) |
CHARACTER |
8 |
FLCETEA |
FLCE A8x: Translation exception address |
| 168 |
(A8) |
CHARACTER |
6 |
|
|
| 174 |
(AE) |
BITSTRING |
1 |
FLCETEA6 |
FLCE AEx: Byte 6 of FlceTEA |
Bit definitions:
|
| |
|
.... 11.. |
FLCEAEFSI |
"X'0C'" Access-exception Fetch/Store indicator: 00 --
not determined. 01 -- store. 10 -- fetch. 11 -- reserved |
| 175 |
(AF) |
BITSTRING |
1 |
FLCETEA7 |
FLCE AFx: Byte 7 of FlceTEA |
Bit definitions:
|
| |
|
.... 1... |
FLCEPEALC |
"X'08'" FLCE AFx: Protection exception due to access-list
control |
| |
|
.... .1.. |
FLCESOPI |
"X'04'" FLCE AFx: Suppress on protection indication |
| |
|
.... ..11 |
FLCETEASTD |
"X'03'" FLCE AFx: Segment table designation for TEA: '00'
- primary STD '01' - STD was AR-qualified '10' - secondary STD '11'
- home STD |
| 168 |
(A8) |
CHARACTER |
8 |
FLCETEASNINFO |
FLCE A8x: ASN Info |
| 168 |
(A8) |
CHARACTER |
6 |
|
|
| 174 |
(AE) |
SIGNED |
2 |
FLCETEASN |
FLCE AEx: ASN |
| 168 |
(A8) |
CHARACTER |
8 |
FLCETEPCINFO |
FLCE A8x: PC Info |
| 168 |
(A8) |
CHARACTER |
4 |
|
|
| 172 |
(AC) |
SIGNED |
4 |
FLCEPCNUM |
FLCE ACx: PC#. Bits 0-10 are 0, bit 11 is 1, and the PC#
is in bits 12-31 |
| 176 |
(B0) |
CHARACTER |
8 |
FLCEMONITORCODE |
FLCE B0x: Monitor Code |
| 184 |
(B8) |
CHARACTER |
4 |
FLCESSID |
FLCE B8x: Subsystem ID word |
| 188 |
(BC) |
CHARACTER |
4 |
FLCEIOINTPARM |
FLCE BCx: I/O interruption parameter |
| 192 |
(C0) |
CHARACTER |
4 |
FLCEIOINTID |
FLCE C0x: I/O interruption ID |
| 196 |
(C4) |
CHARACTER |
4 |
FLCER0C4 |
FLCE C4x: Reserved |
| 200 |
(C8) |
CHARACTER |
16 |
FLCEFACILITIESLIST |
FLCE C8x: Facilities list stored by STFLE. See macro IHAFACL
for a more complete definition of the facilities list. If the facilities
list exceeds 256 bits, only the area mapped by IHAFACL will contain
those additional bits. This 16-byte area matches the area mapped by
FaclBytes0To15 within IHAFACL. |
| 200 |
(C8) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE0 |
FLCE C8x |
Bit definitions:
|
| |
|
1... .... |
FLCEZARCHN3 |
"X'80'" Instructions marked "N3" in the instruction summary
are available on the CPU in ESA/390 mode |
| |
|
1... .... |
FLCEESAMEN3 |
"X'80'" Instructions marked "N3" in the instruction summary
are available on the CPU in ESA/390 mode |
| |
|
.1.. .... |
FLCEZARCHINSTALLED |
"X'40'" The z/Architecture mode is installed on the CPU |
| |
|
.1.. .... |
FLCEESAMEINSTALLED |
"X'40'" The z/Architecture mode is installed on the CPU |
| |
|
..1. .... |
FLCEZARCH |
"X'20'" The z/Architecture mode is active on the CPU |
| |
|
..1. .... |
FLCEESAME |
"X'20'" The z/Architecture mode is active on the CPU |
| |
|
...1 .... |
FLCEIDTEINSTALLED |
"X'10'" IDTE is installed |
| |
|
.... 1... |
FLCEIDTECLEARINGCOMBINEDSEGMENT |
| |
|
|
|
"X'08'" IDTE does clearing of combined entries upon segment-table
entry invalidation |
| |
|
.... .1.. |
FLCEIDTECLEARINGCOMBINEDREGION |
| |
|
|
|
"X'04'" IDTE does clearing of combined entries upon region-table
entry invalidation |
| |
|
.... ..1. |
FLCEASNANDLXREUSEINSTALLED |
"X'02'" The ASN and LX reuse facility is installed on
the CPU |
| |
|
.... ...1 |
FLCESTFLE |
"X'01'" STFLE instruction is available |
| 201 |
(C9) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE1 |
FLCE C9x |
Bit definitions:
|
| |
|
1... .... |
FLCEEDATFEAT |
"X'80'" DAT features |
| |
|
.1.. .... |
FLCESENSERUNNINGSTATUS |
"X'40'" sense-running-status facility |
| |
|
..1. .... |
FLCECONDSSKEINSTALLED |
"X'20'" The conditional SSKE instruction is installed |
| |
|
...1 .... |
FLCECONFIGURATIONTOPOLOGY |
"X'10'" STSI-enhancement for configuration topology |
| |
|
.... 1... |
FLCECQCIF |
"X'08'" 110524 |
| |
|
.... .1.. |
FLCEIPTERANGE |
"X'04'" IPTE-range facility is installed |
| |
|
.... ..1. |
FLCENONQKEYSETTING |
"X'02'" Nonquiescing key-setting facility is installed |
| |
|
.... ...1 |
FLCEAPFT |
"X'01'" The APFT facility is installed / 091111 |
| 202 |
(CA) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE2 |
FLCE CAx |
Bit definitions:
|
| |
|
1... .... |
FLCEETF2 |
"X'80'" Extended translation facility 2 is present |
| |
|
.1.. .... |
FLCECRYPTOASSIST |
"X'40'" The cryptographic assist is present |
| |
|
.1.. .... |
FLCEMESSAGESECURITYASSIST |
"X'40'" The message security assist is present |
| |
|
..1. .... |
FLCELONGDISPLACEMENT |
"X'20'" The long displacement facility is installed in
the z/Architecture mode |
| |
|
...1 .... |
FLCELONGDISPLACEMENTHP |
"X'10'" The long displacement facility has high performance.
Bit FlceLongDisplacement will also be on. |
| |
|
.... 1... |
FLCEHFPMAS |
"X'08'" The HFP Multiply add/subtract facility is installed |
| |
|
.... .1.. |
FLCEEXTENDEDIMMEDIATE |
"X'04'" The extended immediate facility is installed in
the z/Architecture mode |
| |
|
.... ..1. |
FLCEETF3 |
"X'02'" The extended translaction facility 3 is installed
in the z/Architecture mode |
| |
|
.... ...1 |
FLCEHFPUNNORMEXTENSION |
"X'01'" The HFP unnormalized extension facility is installed |
| 203 |
(CB) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE3 |
FLCE CBx |
Bit definitions:
|
| |
|
1... .... |
FLCEETF2E |
"X'80'" ETF2 enhancement is present 031215 |
| |
|
.1.. .... |
FLCESTCKF |
"X'40'" STCKF enhancement is present |
| |
|
..1. .... |
FLCEPARSE |
"X'20'" Parsing enhancement facility is present |
| |
|
.... 1... |
FLCETCSF |
"X'08'" TOD clock steering facility |
| |
|
.... ..1. |
FLCEETF3E |
"X'02'" ETF3 enhancement is present 040512 |
| |
|
.... ...1 |
FLCEECTF |
"X'01'" Extract Cpu Time facility |
| 204 |
(CC) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE4 |
FLCE CCx |
Bit definitions:
|
| |
|
1... .... |
FLCECSSF |
"X'80'" Compare-and-swap-and-store facility |
| |
|
.1.. .... |
FLCECSSF2 |
"X'40'" Compare-and-swap-and-store facility 2 |
| |
|
..1. .... |
FLCEGENERALINSTEXTENSION |
"X'20'" General-Instructions- Extension Facility |
| |
|
.... 1... |
FLCEENHANCEDMONITOR |
"X'08'" The Enhanced Monitor facility is supported. |
| |
|
.... ...1 |
FLCEOBSOLETECPUMEASUREMENT |
"X'01'" Obsolete. Meant CPU-measurement facility supported.
Use FlceCpuMeasurementCounter & FlceCpuMeasurementSampling |
| 205 |
(CD) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE5 |
FLCE CDx |
Bit definitions:
|
| |
|
1... .... |
FLCESETPROGRAMPARM |
"X'80'" Set-Program-Parameter facility is supported |
| |
|
.1.. .... |
FLCEFPSEF |
"X'40'" Floating-point-support enhancement facility |
| |
|
..1. .... |
FLCEDFPF |
"X'20'" Decimal-floating-point facility |
| |
|
...1 .... |
FLCEDFPFHP |
"X'10'" Decimal-floating-point facility high performance |
| |
|
.... 1... |
FLCEPFPO |
"X'08'" PFPO instruction 070424 |
| |
|
.... .1.. |
FLCEDISTINCTOPERANDS |
"X'04'" z196 is the first machine with this facility bit
on. |
| |
|
.... .1.. |
FLCEHIGHWORD |
"X'04'" |
| |
|
.... .1.. |
FLCELOADSTOREONCONDITION |
"X'04'" |
| |
|
.... .1.. |
FLCEPOPULATIONCOUNT |
"X'04'" |
| |
|
.... ...1 |
FLCECMPEF |
"X'01'" Possible future enhancement |
| 206 |
(CE) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE6 |
FLCE CEx |
Bit definitions:
|
| |
|
.1.. .... |
FLCEMISCINSTEXT |
"X'40'" Bit 49 - Miscellaneous instruction extensions
facility. |
| |
|
.1.. .... |
FLCEEXECUTIONHINT |
"X'40'" Bit 49 - Execution hint facility. |
| |
|
.1.. .... |
FLCELOADANDTRAP |
"X'40'" Bit 49 - Load and trap facility. |
| |
|
..1. .... |
FLCECONSTRAINEDTX |
"X'20'" Bit 50 - Constrained Transactional Execution facility.
Even if this bit if on, do not use Constrained TX unless bit CVTTXC
is on (you may alternately check bit PSATXC) |
| |
|
.... .1.. |
FLCELOADSTOREONCOND2 |
"X'04'" Bit 53 - |
| 207 |
(CF) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE7 |
FLCE CFx |
| 208 |
(D0) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE8 |
FLCE D0x bits 64-71 |
Bit definitions:
|
| |
|
1... .... |
FLCERI |
"X'80'" FlceRI |
| |
|
.1.. .... |
FLCECRYPTOAPQAI |
"X'40'" Crypto AP-Queue adapter interruption |
| |
|
...1 .... |
FLCECPUMEASUREMENTCOUNTER |
"X'10'" CPU-measurement counter facility |
| |
|
.... 1... |
FLCECPUMEASUREMENTSAMPLING |
"X'08'" CPU-measurement sampling facility |
| |
|
.... .1.. |
FLCESCLP |
"X'04'" Possible future enhancement |
| |
|
.... ..1. |
FLCEAISI |
"X'02'" AISI facility, bit 70 |
| |
|
.... ...1 |
FLCEAEN |
"X'01'" AEN facility, bit 71 |
| 209 |
(D1) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTE9 |
FLCE D1x bits 72-79 |
Bit definitions:
|
| |
|
1... .... |
FLCEAIS |
"X'80'" AIS facility, bit 72 |
| |
|
.1.. .... |
FLCETRANSACTIONALEXECUTION |
"X'40'" Bit 73 - Transactional Execution facility. Even
if this bit if on, do not use TX unless bit CVTTX is on (you may alternately
check bit PSATX) |
| |
|
.... .1.. |
FLCEMSA4 |
"X'04'" MSA4 facility, bit 77 |
| |
|
.... ..1. |
FLCEEDAT2 |
"X'02'" Bit 78 - Enhanced Dat-2 |
| 210 |
(D2) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTEA |
FLCE D2x |
| 211 |
(D3) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTEB |
FLCE D3x |
| 212 |
(D4) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTEC |
FLCE D4x |
| 213 |
(D5) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTED |
FLCE D5x |
| 214 |
(D6) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTEE |
FLCE D6x |
| 215 |
(D7) |
BITSTRING |
1 |
FLCEFACILITIESLISTBYTEF |
FLCE D7x |
| 216 |
(D8) |
CHARACTER |
16 |
FLCEFACILITIESLIST1 |
FLCE D8x: Facilities list stored by STFLE. It is valid
if on z/OS 2.2 or later. See macro IHAFACL for a more complete definition
of the facilities list. This 16-byte area matches the area mapped
by FaclBytes16To31 within IHAFACL. |
| 232 |
(E8) |
CHARACTER |
8 |
FLCEMCIC |
FLCE E8x: Machine check interruption code |
| 240 |
(F0) |
CHARACTER |
4 |
FLCEMCICE |
FLCE F0x: Machine check interruption code extension |
| 244 |
(F4) |
CHARACTER |
4 |
FLCEEDCODE |
FLCE F4x: External damage code |
| 248 |
(F8) |
CHARACTER |
8 |
FLCEFSA |
FLCE F8x: Failing storage address |
| 256 |
(100) |
ADDRESS |
8 |
FLCEEMFCTRARRAYADDR |
FLCE 100x: The enhanced monitor facility counter array
origin |
| 264 |
(108) |
SIGNED |
4 |
FLCEEMFCTRARRAYSIZE |
FLCE 108x: The enhanced monitor facility counter array
dimension |
| 268 |
(10C) |
SIGNED |
4 |
FLCEEMFEXCEPTIONCNT |
FLCE 10Cx: The enhanced monitor facility exception count |
| 272 |
(110) |
CHARACTER |
8 |
FLCEBEA |
FLCE 110x: Breaking event address |
| 280 |
(118) |
CHARACTER |
8 |
FLCER118 |
FLCE 118x: Reserved |
| 288 |
(120) |
CHARACTER |
16 |
FLCEROPSW |
FLCE 120x: Restart old PSW |
| 304 |
(130) |
CHARACTER |
16 |
FLCEEOPSW |
FLCE 130x: External old PSW |
| 320 |
(140) |
CHARACTER |
16 |
FLCESOPSW |
FLCE 140x: SVC old PSW |
| 336 |
(150) |
CHARACTER |
16 |
FLCEPOPSW |
FLCE 150x: Program old PSW |
| 352 |
(160) |
CHARACTER |
16 |
FLCEMOPSW |
FLCE 160x: Machine check old PSW |
| 368 |
(170) |
CHARACTER |
16 |
FLCEIOPSW |
FLCE 170x: I/O old PSW |
| 384 |
(180) |
CHARACTER |
32 |
FLCER180 |
FLCE 180x: reserved |
| 416 |
(1A0) |
CHARACTER |
16 |
FLCERNPSW |
FLCE 1A0x: Restart new PSW |
| 432 |
(1B0) |
CHARACTER |
16 |
FLCEENPSW |
FLCE 1B0x: External new PSW |
| 448 |
(1C0) |
CHARACTER |
16 |
FLCESNPSW |
FLCE 1C0x: SVC new PSW |
| 464 |
(1D0) |
CHARACTER |
16 |
FLCEPNPSW |
FLCE 1D0x: Program new PSW |
| 480 |
(1E0) |
CHARACTER |
16 |
FLCEMNPSW |
FLCE 1E0x: Machine check new PSW |
| 496 |
(1F0) |
CHARACTER |
16 |
FLCEINPSW |
FLCE 1F0x: I/O new PSW |
| 496 |
(1F0) |
X'200' |
0 |
FLCESAME_LEN |
"*-FLCESAME" |