POWER-based-architecture-unique timer access
The POWER® family and POWER2 processor architectures include two special-purpose registers (an upper register and a lower register) that contain a high-resolution timer.
Note: The following discussion applies only to the POWER family and POWER2 architectures (and the 601
processor chip). The code examples will function correctly in a POWER-based
system, but some of the instructions will be simulated. Because the purpose
of accessing the processor timer is to obtain high-precision times with low
overhead, simulation makes the results much less useful.
The upper register of the POWER family and POWER2 processor architectures contains time in seconds, and the lower register contains a count of fractional seconds in nanoseconds. The actual precision of the time in the lower register depends on its update frequency, which is model-specific.