Dynamic processor sparing allows inactive processors to act as dynamic spares in environments with Capacity on Demand (CoD). Memory sparing occurs when on-demand inactive memory is automatically activated by the system to temporarily replace failed memory until a service action can be performed.
Processor sparing helps minimize the impact to server performance caused by a failed processor. An inactive processor is activated if a failing processor reaches a predetermined error threshold, thus helping to maintain performance and improve system availability. Dynamic processor sparing happens dynamically and automatically when using dynamic logical partitioning (DLPAR) and the failing processor is detected prior to failure. If not detected prior to failure or when not using DLPAR, a reboot of the system or partition activates an alternate processor from the inactive spares. You can then re-establish required performance levels without waiting for parts to arrive on-site. Dynamic processor sparing does not require the purchase of an activation code; it requires only that the system have inactive CUoD processors available.
Memory sparing occurs only when inactive CoD memory is present in a system and when an entire memory feature becomes unusable. During an initial program load (IPL), failed memory parts are taken out of use and inactive CoD memory is activated in place of the failed part without operational intervention.
Memory sparing is one example of the reliability, availability, and service (RAS) capabilities available for IBM® Systems and IBM eServer™ hardware products. Other capabilities include bit steering and bit sparing.
Memory sparing is available on the model 9119-590 and 9119-595, as well as the model 9406-595. Memory sparing is also available on the model 9406-MMA and 9117-MMA; however, it is limited to the first feature failure on those models. When all the memory is operational again, then another first feature failure is spared.
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