Memory virtualization parameters

Size of the dynamic paging area

A central parameter influencing the capability of z/VM® to make memory available to virtual systems in an efficient way is the size of the dynamic paging area (DPA). The larger the DPA, the more page frames are available for backing virtual memory pages, reducing the need to write pages to a paging disk when page frames are needed for supporting the virtual memory of other virtual systems. z/VM dynamically determines the size of the DPA when initially loaded, by first reserving space for its own data structures in real memory, and then assigning the remaining real memory for the DPA. Thus the size of the DPA closely depends on the size of real memory available to z/VM. In our tests, we scaled down the amount of memory available to z/VM at IPL time, resulting in a smaller DPA and causing more pressure on the z/VM memory and paging subsystem in support of virtual system memory.

Memory overcommitment factor

A common definition of memory overcommitment is to add up the defined sizes of all virtual memory consumers, and relate that to the amount of real memory available:

( ∑ defined virtual memory of each virtual system ) : z/VM real memory

In this paper, we decided not to use this definition of memory overcommitment, because it does not eliminate the effects resulting from arbitrarily over-sizing virtual system memory.

Instead, we determined the memory overcommitment ratio as the ratio of instantiated memory related to resident memory:

ocr = ∑ IM_x : ∑ RM_x (x=1...n)

with:

ocr

memory overcommitment ratio

IM_x

instantiated memory of virtual system x

RM_x

resident memory of virtual system x

n

number of virtual systems considered

With this definition, a memory overcommit ratio of 1:1 means that z/VM system provides exactly the amount of memory that is in use by the considered set of virtual systems. A value larger than 1:1, such as for example 1.2:1, would mean that a shortage of real memory exists, or – in other words – that the amount of resident memory that z/VM maintains for the virtual systems is less than the amount of virtual memory in use by the virtual systems, that is, their aggregated instantiated memory.

When the memory overcommitment of all active virtual systems is to be considered in a memory constrained situation, the sum of the resident memory of all virtual system equals the z/VM DPA size. In this case, the above formula could be simplified to:

ocr = ∑ IM_x : DPAsize (x=1...n)

with:

DPAsize

z/VM DPA size (see the description of DPA size in z/VM performance metrics)

One challenge of this project was to determine how performance was impacted in memory constrained situations, namely when the amount of real memory supporting the virtual memory in use by the combined workload set was limited to such an extent that the workloads started to report errors. At this point the runs were considered as failed, and not further included in the analysis.

Efficiency of memory management

The algorithms in use by operating systems for managing memory are very sophisticated. They have significant impact on the performance of processes working with virtual memory. With z/VM 6.3, memory management was completely redesigned. For details, see z/VM 6.3 CP Planning and Administration.

In our tests, we compared the performance of the combined workload set when executed under z/VM 6.3, as opposed to z/VM 6.2.

Efficiency of the paging subsystem

Another factor influencing virtual memory access performance is the efficiency of the paging subsystem. The more efficiently pages can be transferred between paging space on disk and the DPA, the faster virtual memory can be made available for use by virtual systems.

In our tests, we inspected the performance of running the combined workload set when using EDEV-SCSI based paging devices as opposed to using ECKD™ based paging devices. This comparison was of particular interest, because z/VM is able to overlap I/O operations on EDEV-SCSI based paging devices, but not on ECKD based paging devices.

System z® processor and memory organization

In our tests, the z/VM system was operated within a logical partition (LPAR) defined on a System z central processor complex (CPC). For details, see Host system.

For System z CPCs, a packaging design based on so called books is used. A book is a hardware container that – among other elements – contains a multiple chip module (MCM) and memory. The MCM contains a number of chips, and each chip hosts several processor units (PUs), along with PU-specific caches as well as shared caches. The MCM further contains storage control (SC) chips that provide connectivity among PUs and to other books, particularly for access to memory. The SCs also host another level of caches that are shared by all PUs on the MCM.

This hierarchical architecture implies that memory is distributed across books, and caches are distributed across PUs, processor chips, and SCs. When memory is accessed across PUs, chips and books, different access times and latencies might result. We did not make efforts to detect or evaluate such situations as a source for performance variations.