RS format
The operand fields of RS-format instructions designate two registers,
and a virtual storage address (coded as an implicit address or an
explicit address).

In the Insert Characters under Mask (ICM) and the Store Characters under Mask (STCM) instructions, a 4 bit mask, with a value 0 through 15, replaces the second register specifications.

Symbols used to represent registers (see REG4
, REG6
,
and BASE
in the instruction labeled ALPHA2
in
the examples) are assumed to be equated to absolute values 0 - 15.
Symbols used to represent implicit addresses (see AREA
and IMPLICIT
in
the instructions labeled BETA1
and DELTA2
in
the examples) can be either relocatable or absolute.
Symbols used to represent displacements (see DISPL
in
the instruction labeled BETA2
in the examples) in
explicit addresses are assumed to be equated to absolute values 0
- 4095.
Examples
Sample Program - LRSAMP06 - HLASM Page 3
Active Usings: None
Loc Object Code Addr1 Addr2 Stmt Source Statement HLASM R6.0 2015/02/26 18.53
2 ***********************************************************************
3 * *
4 * Licensed Materials - Property of IBM *
5 * *
6 * 5696-234 *
7 * *
8 * Copyright IBM Corporation 2008, 2015 All Rights Reserved. *
9 * *
10 * US Government Users Restricted Rights - Use, duplication *
11 * or disclosure restricted by GSA ADP Schedule Contract *
12 * with IBM Corp. *
13 * *
14 ***********************************************************************
00000000 00000000 00000030 15 LPSAMP06 CSECT
00000003 16 R3 EQU 3
00000004 17 R4 EQU 4
00000006 18 R6 EQU 6
0000000C 19 R12 EQU 12
0000000E 20 R14 EQU 14
0000000F 21 R15 EQU 15
0000000C 22 BASE EQU 12
R:C 00000000 23 USING LPSAMP06,BASE Assign the base register
00000000 18CF 24 LR R12,R15
00000002 9846 C014 00000014 25 ALPHA1 LM 4,6,20(12)
00000006 9846 C014 00000014 26 ALPHA2 LM R4,R6,20(BASE)
0000000A 9046 C020 00000020 27 BETA1 STM 4,6,AREA
0000000E 9046 C014 00000014 28 BETA2 STM 4,6,DISPL(BASE)
00000012 8920 000F 0000000F 29 GAMMA1 SLL 2,15
00000016 BF3E A400 00000400 30 DELTA1 ICM 3,B'1110',1024(10)
0000001A BF3D C02C 0000002C 31 DELTA2 ICM R3,MASK,IMPLICIT
0000001E 07FE 32 BR R14 Return
0000000D 33 MASK EQU B'1101'
00000020 0000000000000000 34 AREA DC 3F'0'
00000014 35 DISPL EQU 20
0000002C C6D9C5C4 36 IMPLICIT DC C'FRED'
37 END
When assembled, the object code for the instruction labeled
ALPHA1
(statement 25), in hexadecimal, is: 9846C014
where:
98 |
Is the operation code |
4 |
Is register R₁ |
6 |
Is register R₃ |
C |
Is base register B₁ |
014 |
Is displacement D₁ from base register B₁ |
When assembled, the object code for the instruction labeled
DELTA1
(statement 30), in hexadecimal, is: BF3EA400
where:
BF |
Is the operation code |
3 |
Is register R₁ |
E |
Is mask M₃ |
A |
Is base register B₁ |
400 |
Is displacement D₁ from base register B₁ |