Instruction characteristics
A code of b'...1....'
generates output with the following structure:
Origin | Length | Contents |
---|---|---|
0 | 1 | Instruction length (in bytes) |
1 | 1 | Instruction format - see Instruction Formats for values |
2 | 1 | Sub-format - see Instruction Formats for values |
3 | .1 each | Principles of Operations Notes: |
c - Condition code set | ||
i - Interruptible instruction | ||
n - New condition code loaded | ||
p - Privileged instruction | ||
q - Semi-privileged instruction | ||
x - Execution in problem state and supervisor state differs | ||
y - Condition code may be set | ||
z - Condition code is unpredictable | ||
4 | .1 each | Additional Information: |
Branch Instruction | ||
Space-switch Operation | ||
Dependent on Current PSW Address | ||
5 | .1 each | Possible Condition Codes Set: |
Condition Code 0 | ||
Condition Code 1 | ||
Condition Code 2 | ||
Condition Code 3 | ||
6 | 2 | Reserved for future use |
Format | Name | Sub-format | Operands |
---|---|---|---|
0 | Invalid | - | - |
1 | E | 1 | |
2 | RR | 1 | R1,R2 |
2 | I1 | ||
3 | R1 | ||
4 | M1,R2 | ||
3 | QST | 1 | VR1,QR3,RS2(RT2) |
2 | M1,QR3,RS2(RT2) | ||
4 | QV | 1 | VR1,QR3,VR2 |
2 | M1,QR3,VR2 | ||
3 | VR1,QR2 | ||
5 | RRE | 1 | R1 |
2 | R1,R2 | ||
3 | |||
6 | RS | 1 | R1,R3,D2(B2) |
2 | R1,D2(B2) | ||
3 | R1,M3,D2(B2) | ||
7 | RX | 1 | R1,D2(X2,B2) |
2 | M1,D2(X2,B2) | ||
8 | S | 1 | D2(B2) |
2 | |||
9 | SI | 1 | D1(B1),I2 |
10 | VR | 1 | VR1,QR3,R2 |
2 | VR1,QR2 | ||
3 | VR1 | ||
11 | VS | 1 | RS2 |
12 | VST | 1 | VR1,VR3,RST(RT2) |
2 | VR1,RS2(RT2) | ||
3 | M1,VR3,RS2(RT2) | ||
13 | VV | 1 | VR1,VR3,VR2 |
2 | VR1,VR2 | ||
3 | M1,VR3,VR2 | ||
4 | VR1 | ||
14 | RSEV | 1 | VR1,VR3,D2(B2) |
15 | SS | 1 | D1(L1,B1),D2(L2,B2) |
2 | D1(L1,B1),D2(B2) | ||
3 | D1(L1,B1),D2(B2),I3 | ||
4 | D1(R1,B1),D2(B2),R3 | ||
5 | R1,D2(B2),R3,D4(B4) | ||
6 | R1,R3,D2(B2),D4(B4) | ||
7 | D1(B1),D2(L2,B2) | ||
16 | SSE | 1 | D1(B1),D2(B2) |
17 | RI | 1 | R1,I2 |
2 | M1,I2 | ||
18 | RSI | 1 | R1,R3,I2 |
19 | RRF | 1 | R1,R3,R2,M4 |
2 | R1,M3,R2 | ||
3 | R1,R3,R2 | ||
4 | R1,R2,R3 | ||
5 | R1,R3,R2 | ||
6 | R1,M3,R2,M4 | ||
7 | R1,R2,M4 | ||
8 | R1,R2,R3,M4 | ||
9 | R1,R2,M3,M4 | ||
20 | RXE | 1 | R1,D2(X2,B2),M3 |
21 | RIL | 1 | R1,I2 |
2 | M1,I2 | ||
22 | RIE | 1 | R1,R3,I2 |
2 | R1,I2,M3 | ||
3 | R1,R2,M3,I4 | ||
4 | R1,I2,M3,I4 | ||
5 | R1,R2,I3,I4,I5 | ||
6 | R1,I2,M3 | ||
23 | RXF | 1 | R1,R3,D2(X2,B2) |
24 | RSE | 1 | R1,R3,D2(B2) |
2 | R1,M3,D2(B2) | ||
25 | RSL | 1 | D1(L1,B1) |
2 | R1,D2(L2,B2),M3 | ||
26 | RXY | 1 | R1,D2(X2,B2) |
2 | M1,D2(X2,B2) | ||
27 | RSY | 1 | R1,R3,D2(B2) |
2 | R1,M3,D2(B2) | ||
3 | R1,D2(B2),M3 | ||
28 | SIY | 1 | D1(B1),I2 |
29 | SSF | 1 | D1(B1),D2(B2),R3 |
2 | R3,D1(B1),D2(B2) | ||
30 | RRD | 1 | R1,R2,R3 |
31 | RIS | 1 | R1,I2,M3,D4(B4) |
32 | RRS | 1 | R1,R2,M3,D4(B4) |
33 | SIL | 1 | D1(B1),I2 |
34 | IE | 1 | I1,I2 |
35 | MII | 1 | MI,I2,I3 |
36 | SMI | 1 | MI,I2,D3(B3) |
37 | VRI | 1 | V1,I2,M3 |
2 | V1,I2,I3,M4 | ||
3 | V1,V3,I2,M4 | ||
4 | V1,V2,V3,I4,M5 | ||
5 | V1,V2,I3,M4,M5 | ||
6 | V1,V2,V3,I4,M5 | ||
7 | V1,V2,I3,I4,M5 | ||
8 | V1,I2,I3 | ||
9 | V1,R2,I3,M4 | ||
38 | VRR | 1 | V1,V2,M3,M4,M5 |
2 | V1,V2,V3,M4,M5 | ||
3 | V1,V2,V3,M4,M5,M6 | ||
4 | V1,V2,V3,V4,M5,M6 | ||
5 | V1,V2,V3,V4,M5,M6 | ||
6 | V1,R2,V3 | ||
7 | V1 | ||
8 | V1,V2,V3 | ||
9 | R1,V2,M3 | ||
10 | V1,V2,M3,M4 | ||
11 | V1,V2,M3 | ||
39 | VRS | 1 | V1,V3,D2(B2),M4 |
2 | V1,R3,D2(B2),M4 | ||
3 | R1,V3,D2(B2),M4 | ||
4 | V1,R3,D2(B2) | ||
40 | VRV | 1 | V1,D2(V2,B2),M3 |
41 | VRX | 1 | V1,D2(X2,B2),M3 |
42 | VSI | 1 | V1,D2(B2),I3 |