POWER® family and PowerPC® architecture overview

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A POWER® family or PowerPC® microprocessor contains a branch processor, a fixed-point processor, and a floating-point processor.

A POWER® family or PowerPC® microprocessor contains the sequencing and processing controls for instruction fetch, instruction execution, and interrupt action, and implements the instruction set, storage model, and other facilities defined in the POWER® family and PowerPC® architectures.

A POWER® family or PowerPC® microprocessor contains a branch processor, a fixed-point processor, and a floating-point processor. The microprocessor can execute the following classes of instructions:
  • Branch instructions
  • Fixed-point instructions
  • Floating-point instructions

The following diagram illustrates a logical representation of instruction processing for the PowerPC® microprocessor.

Figure 1. Logical Processing Model. The process begins at the top with Branch Processing, which branches to either fixed-point or float-point processing. These processes send and receive data from storage. Storage will also send more instructions to Branch Processing at the top of the diagram.

The following table shows the registers for the PowerPC® user instruction set architecture. These registers are in the CPU that are used for 32-bit applications and are available to the user.

Register Bits Available
Condition Register (CR) 0-31
Link Register (LR) 0-31
Count Register (CTR) 0-31
General Purpose Registers 00-31 (GPR) 0-31 for each register
Fixed-Point Exception Register (XER) 0-31
Floating-Point Registers 00-31 (FPR) 0-63 for each register
Floating Point Status and Control Register (FPSCR) 0-31

The following table shows the registers of the POWER® family user instruction set architecture. These registers are in the CPU that are used for 32-bit applications and are available to the user.

Register Bits Available
Condition Register (CR) 0-31
Link Register (LR) 0-31
Count Register (CTR) 0-31
General Purpose Registers 00-31 (GPR) 0-31 for each register
Multiply-Quotient Register (MQ) 0-31
Fixed-Point Exception Register (XER) 0-31
Floating-Point Registers 00-31 (FPR) 0-63 for each register
Floating Point Status and Control Register (FPSCR) 0-31

The processing unit is a word-oriented, fixed-point processor functioning in tandem with a doubleword-oriented, floating-point processor. The microprocessor uses 32-bit word-aligned instructions. It provides for byte, halfword, and word operand fetches and stores for fixed point, and word and doubleword operand fetches and stores for floating point. These fetches and stores can occur between main storage and a set of 32 general-purpose registers, and between main storage and a set of 32 floating-point registers.