frsp (Floating Round to Single Precision) instruction

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Purpose

Rounds a 64-bit, double precision floating-point operand to single precision and places the result in a floating-point register.

Syntax

Bits Value
0-5 63
6-10 FRT
11-15 ///
16-20 FRB
21-30 12
31 Rc
Item Description
frsp FRT, FRB
frsp. FRT, FRB

Description

The frsp instruction rounds the 64-bit, double-precision floating-point operand in floating-point register (FPR) FRB to single precision, using the rounding mode specified by the Floating Rounding Control field of the Floating-Point Status and Control Register, and places the result in the target FPR FRT.

The Floating-Point Result Flags Field of the Floating-Point Status and Control Register is set to the class and sign of the result, except for Invalid Operation (SNaN), when Floating-Point Status and Control Register Floating-Point Invalid Operation Exception Enable bit is 1.

The frsp instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.

Item Description
Syntax Form Floating-Point Status and Control Register Record Bit (Rc) Condition Register Field 1
frsp C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN 0 None
frsp. C,FL,FG,FE,FU,FR,FI,OX,UX, XX,VXSNAN 1 FX,FEX,VX,OX

The two syntax forms of the frsp instruction always affect the Floating-Point Status and Control Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating-Point Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.

Notes:
  1. The frsp instruction uses the target register of a previous floating-point arithmetic operation as its source register (FRB). The frsp instruction is said to be dependent on the preceding floating-point arithmetic operation when it uses this register for source.
  2. Less than two nondependent floating-point arithmetic operations occur between the frsp instruction and the operation on which it is dependent.
  3. The magnitude of the double-precision result of the arithmetic operation is less than 2**128 before rounding.
  4. The magnitude of the double-precision result after rounding is exactly 2**128.

Error Result

If the error occurs, the magnitude of the result placed in the target register FRT is 2**128:


X'47F0000000000000' or X'C7F0000000000000'

This is not a valid single-precision value. The settings of the Floating-Point Status and Control Register and the Condition Register will be the same as if the result does not overflow.

Avoiding Errors

If the above error will cause significant problems in an application, either of the following two methods can be used to avoid the error.

  1. Place two nondependent floating-point operations between a floating-point arithmetic operation and the dependent frsp instruction. The target registers for these nondependent floating-point operations should not be the same register that the frsp instruction uses as source register FRB.
  2. Insert two frsp operations when the frsp instruction may be dependent on an arithmetic operation that precedes it by less than three floating-point instructions.

Either solution will degrade performance by an amount dependent on the particular application.

Parameters

Item Description
FRT Specifies target floating-point register for operation.
FRB Specifies source floating-point register for operation.

Examples

  1. The following code rounds the contents of FPR 4 to single precision, places the result in a FPR 6, and sets the Floating-Point Status and Control Register to reflect the result of the operation: 
    
# Assume FPR 4 contains 0xC053 4000 0000 0000.
# Assume FPSCR = 0.
frsp 6,4
# FPR 6 now contains 0xC053 4000 0000 0000.
# FPSCR now contains 0x0000 8000.
  2. The following code rounds the contents of FPR 4 to single precision, places the result in a FPR 6, and sets the Floating-Point Status and Control Register and Condition Register Field 1 to reflect the result of the operation: 
    
# Assume CR contains 0x0000 0000.
# Assume FPR 4 contains 0xFFFF FFFF FFFF FFFF.
# Assume FPSCR = 0.
frsp. 6,4
# FPR 6 now contains 0xFFFF FFFF E000 0000.
# FPSCR now contains 0x0001 1000.
# CR now contains 0x0000 0000.