dcbtst (Data Cache Block Touch for Store) instruction
Purpose
Allows a program to request a cache block fetch before it is actually needed by the program.
Syntax
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | TH |
| 11-15 | RA |
| 16-20 | RB |
| 21-30 | 246 |
| 31 | / |
Description
The dcbtst instruction improves performance by anticipating a store to the addressed byte. The block containing the byte addressed by the effective address (EA) is fetched into the data cache before the block is needed by the program. The program can later perform stores to the block and may not experience the added delay caused by fetching the block into the cache. Executing the dcbtst instruction does not invoke the system error handler.
The dcbtst instruction calculates an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB. If the RA field is 0, EA is the sum of the contents of RB and 0.
Consider the following when using the dcbtst instruction:
- If the EA specifies a direct store segment address, the instruction is treated as a no-op.
- The access is treated as a load from the addressed cache block with respect to protection. If protection does not permit access to the addressed byte, the dcbtst instruction performs no operations.
- If a program does not need to store to the data cache block, use the dcbt (Data Cache Block Touch) instruction.
The dcbtst instruction has one syntax form and does not affect Condition Register field 0 or the Fixed-Point Exception register.
The Touch Hint (TH) field is used to provide a hint that the program will probably store soon to the storage locations specified by the EA and the TH field. The hint is ignored for locations that are caching-inhibited or guarded. The encodings of the TH field depend on the target architecture selected with the -m flag or the .machine pseudo-op. The encodings of the TH field are the same as for the dcbt instruction.
The dcbtst instruction serves as both a basic and extended mnemonic. The dcbtst mnemonic with three operands is the basic form, and the dcbtst with two operands is the extended form. In the extended form, the TH operand is omitted and assumed to be 0. The encodings of the TH field on POWER5™ and subsequent architectures are as follows:
| TH Values | Description |
|---|---|
| 0000 | The program will probably store to the byte addressed by EA. |
| 0001 | The program will probably store to the data stream consisting of the block containing the byte addressed by EA and an unlimited number of sequentially following blocks. The sequentially preceding blocks are the bytes addressed by EA + n * block_size, where n = 0, 1, 2, and so on. |
| 0011 | The program will probably store to the data stream consisting of the block containing the byte addressed by EA and an unlimited number of sequentially preceding blocks. The sequentially preceding blocks are the bytes addressed by EA - n * block_size where n = 0, 1, 2, and so on. |
| 1000 | The dcbt instruction provides a hint that describes certain attributes of a data stream, and optionally indicates that the program will probably store to the stream. The EA is interpreted as described in EA Encoding when TH=0b1000 . |
| 1010 | The dcbt instruction provides a hint that describes certain attributes of a data stream, or indicates that the program will probably store to data streams that have been described using dcbt instructions in which TH[0] = 1 or probably no longer store to such data streams. The EA is interpreted as described in EA Encoding when TH=0b1010 |
Parameters
| Item | Description |
|---|---|
| RA | Specifies source general-purpose register for operation. |
| RB | Specifies source general-purpose register for operation. |
| TH | Indicates when a sequence of data cache blocks might be modified. |