bcctr or bcc (Branch Conditional to Count Register) instruction

Purpose

Conditionally branches to the address contained within the Count Register.

Syntax

Bits	Value
0 - 5	19
6 - 10	BO
11 - 15	BI
16 - 18	///
19 - 20	BH
21 - 30	528
31	LK

PowerPC®
bcctr	BO, BI, BH
bcctrl	BO, BI, BH

POWER® family
bcc	BO, BI, BH
bccl	BO, BI, BH

Description

The bcctr and bcc instructions conditionally branch to an instruction specified by the branch target address contained within the Count Register. The branch target address is the concatenation of Count Register bits 0-29 and b'00'.

The bcctr and bcc instructions have two syntax forms. Each syntax form has a different effect on the Link bit and Link Register.

Item	Description
Syntax Form	Absolute Address Bit (AA)	Fixed-Point Exception Register	Link Bit (LK)	Condition Register Field 0
bcctr	None	None	0	None
bcctrl	None	None	1	None
bcc	None	None	0	None
bccl	None	None	1	None

The two syntax forms of the bcctr and bcc instructions never affect the Fixed-Point Exception Register or Condition Register Field 0. If the Link bit is 1, then the effective address of the instruction following the branch instruction is placed into the Link Register.

The Branch Option field (BO) is used to combine different types of branches into a single instruction. Extended mnemonics are provided to set the Branch Option field automatically.

The encoding for the BO field is defined in PowerPC® architecture. The following list gives brief descriptions of the possible values for this field using pre-V2.00 encoding:

BO	Description
`0000y`	Decrement the CTR; then branch if the decremented CTR is not 0 and the condition is False.
`0001y`	Decrement the CTR; then branch if the decremented CTR is 0 and the condition is False.
`001zy`	Branch if the condition is False.
`0100y`	Decrement the CTR; then branch if bits the decremented CTR is not 0 and the condition is True.
`0101y`	Decrement the CTR; then branch if the decremented CTR is 0 and the condition is True.
`011zy`	Branch if the condition is True.
`1z00y`	Decrement the CTR; then branch if the decremented CTR is not 0.
`1z01y`	Decrement the CTR; then branch if the decremented CTR is 0.
`1z1zz`	Branch always.

In the PowerPC® architecture, the bits are as follows:

The z bit denotes a bit that must be 0. If the bit is not 0, the instruction form is invalid.
The y bit provides a hint about whether a conditional branch is likely to be taken. The value of this bit can be either 0 or 1. The default value is 0.

In the POWER® family Architecture, the z and y bits can be either 0 or 1.

The encoding for the BO field using V2.00 encoding is briefly described below:

Table 1. BO Field Values Using V2.00 Encoding
BO	Description
`0000z`	Decrement the CTR; then branch if the decremented CTR is not 0 and the condition is False.
`0001z`	Decrement the CTR; then branch if the decremented CTR is 0 and the condition is False.
`001at`	Branch if the condition is False.
`0100z`	Decrement the CTR; then branch if bits the decremented CTR is not 0 and the condition is True.
`0101z`	Decrement the CTR; then branch if the decremented CTR is 0 and the condition is True.
`011at`	Branch if the condition is True.
`1a00t`	Decrement the CTR; then branch if the decremented CTR is not 0.
`1a01t`	Decrement the CTR; then branch if the decremented CTR is 0.
`1z1zz`	Branch always.

The a and t bits of the BO field can be used by software to provide a hint about whether a branch is likely to be taken, as shown below:

at	Hint
00	No hint is given.
01	Reserved
10	The branch is very likely not to be taken.
11	The branch is very likely to be taken.

For more information, see the IBM Power ISA PDF.

The Branch Hint field (BH) is used to provide a hint about the use of the instruction, as shown below:

BH	Hint
00	The instruction is not a subroutine return; the target address is likely to be the same as the target address used the preceding time the branch was taken.
01	Reserved
10	Reserved
11	The target address is not predictable.

Parameters

Item	Description
BO	Specifies Branch Option field.
BI	Specifies bit in Condition Register for condition comparison.
BIF	Specifies the Condition Register field that specifies the Condition Register bit (LT, GT, EQ, or SO) to be used for condition comparison.
BH	Provides a hint about the use of the instruction.

Examples

The following code branches from a specific address, dependent on a bit in the Condition Register, to the address contained in the Count Register, and no branch hints are given:


bcctr 0x4,0,0
cror 31,31,31
# Branch occurs if LT bit in the Condition Register is 0.
# The branch will be to the address contained in
# the Count Register.
bcctrl 0xC,1,0
return: cror 31,31,31
# Branch occurs if GT bit in the Condition Register is 1.
# The branch will be to the address contained in 
# the Count Register.
# The Link register now contains the address of return.