Instruction fields

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The set of instruction fields.

Item Description
AA (30) Specifies an Absolute Address bit:
0
Indicates an immediate field that specifies an address relative to the current instruction address. For I-form branches, the effective address of the branch target is the sum of the LI field sign-extended to 64 bits (PowerPC®) or 32 bits (POWER® family) and the address of the branch instruction. For B-form branches, the effective address of the branch target is the sum of the BD field sign-extended to 64 bits (PowerPC®) or 32 bits (POWER® family) and the address of the branch instruction.
1
Indicates an immediate field that specifies an absolute address. For I-form branches, the effective address of the branch target is the LI field sign-extended to 64 bits (PowerPC®) or 32 bits (POWER® family). For B-form branches, the effective address of the branch target is the BD field sign-extended to 64 bits (PowerPC®) or 32 bits (POWER® family).
BA (11:15) Specifies a bit in the Condition Register (CR) to be used as a source.
BB (16:20) Specifies a bit in the CR to be used as a source.
BD (16:29) Specifies a 14-bit signed two's-complement branch displacement that is concatenated on the right with 0b00 and sign-extended to 64 bits (PowerPC®) or 32 bits (POWER® family). This is an immediate field.
BF (6:8) Specifies one of the CR fields or one of the Floating-Point Status and Control Register (FPSCR) fields as a target. For POWER® family, if i=BF(6:8), then the i field refers to bits i*4 to (i*4)+3 of the register.
BFA (11:13) Specifies one of the CR fields or one of the FPSCR fields as a source. For POWER® family, if j=BFA(11:13), then the j field refers to bits j*4 to (j*4)+3 of the register.
BI (11:15) Specifies a bit in the CR to be used as the condition of a branch conditional instruction.
BO (6:10) Specifies options for the branch conditional instructions. The possible encodings for the BO field are:
BO
Description
0000x
Decrement Count Register (CTR). Branch if the decremented CTR value is not equal to 0 and the condition is false.
0001x
Decrement CTR. Branch if the decremented CTR value is 0 and the condition is false.
001xx
Branch if the condition is false.
0100x
Decrement CTR. Branch if the decremented CTR value is not equal to 0 and the condition is true.
0101x
Decrement CTR. Branch if the decremented CTR value is equal to 0 and the condition is true.
011x
Branch if the condition is true.
1x00x
Decrement CTR. Branch if the decremented CTR value is not equal to 0.
1x01x
Decrement CTR. Branch if bits 32-63 of the CTR are 0 (PowerPC®) or branch if the decremented CTR value is equal to 0 (POWER® family).
1x1xx
Branch always.
BT (6:10) Specifies a bit in the CR or in the FPSCR as the target for the result of an instruction.
D (16:31) Specifies a 16-bit signed two's-complement integer that is sign-extended to 64 bits (PowerPC®) or 32 bits (POWER® family). This is an immediate field.
EO (21:30) Specifies a10-bit extended op code used in X-form instructions.
EO' (22:30) Specifies a 9-bit extended op code used in XO-form instructions.
FL1 (16:19) Specifies a 4-bit field in the svc (Supervisor Call) instruction.
FL2 (27:29) Specifies a 3-bit field in the svc instruction.
FLM (7:14) Specifies a field mask that specifies the FPSCR fields which are to be updated by the mtfsf instruction:
Bit
Description
7
FPSCR field 0 (bits 00:03)
8
FPSCR field 1 (bits 04:07)
9
FPSCR field 2 (bits 08:11)
10
FPSCR field 3 (bits 12:15)
11
FPSCR field 4 (bits 16:19)
12
FPSCR field 5 (bits 20:23)
13
FPSCR field 6 (bits 24:27)
14
FPSCR field 7 (bits 28:31)
FRA (11:15) Specifies a floating-point register (FPR) as a source of an operation.
FRB (16:20) Specifies an FPR as a source of an operation.
FRC (21:25) Specifies an FPR as a source of an operation.
FRS (6:10) Specifies an FPR as a source of an operation.
FRT (6:10) Specifies an FPR as the target of an operation.
FXM (12:19) Specifies a field mask that specifies the CR fields that are to be updated by the mtcrf instruction:
Bit
Description
12
CR field 0 (bits 00:03)
13
CR field 1 (bits 04:07)
14
CR field 2 (bits 08:11)
15
CR field 3 (bits 12:15)
16
CR field 4 (bits 16:19)
17
CR field 5 (bits 20:23)
18
CR field 6 (bits 24:27)
19
CR field 7 (bits 28:31)
I (16:19) Specifies the data to be placed into a field in the FPSCR. This is an immediate field.
LEV (20:26) This is an immediate field in the svc instruction that addresses the svc routine by b'1' || LEV || b'00000 if the SA field is equal to 0.
LI (6:29) Specifies a 24-bit signed two's-complement integer that is concatenated on the right with 0b00 and sign-extended to 64 bits (PowerPC®) or 32 bits (POWER® family). This is an immediate field.
LK (31) Link bit:
0
Do not set the Link Register.
1
Set the Link Register. If the instruction is a branch instruction, the address of the instruction following the branch instruction is placed in the Link Register. If the instruction is an svc instruction, the address of the instruction following the svc instruction is placed into the Link Register.
MB (21:25) and ME (26:30) (POWER® family) Specifies a 32-bit string. This string consists of a substring of ones surrounded by zeros, or a substring of zeros surrounded by ones. The encoding is:
MB (21:25)
Index to start bit of substring of ones.
ME (26:30)
Index to stop bit of substring of ones.

Let mstart=MB and mstop=ME:
If mstart < mstop + 1 then
          mask(mstart..mstop) = ones
          mask(all other) = zeros
If mstart = mstop + 1 then
          mask(0:31) = ones
If mstart > mstop + 1 then
          mask(mstop+1..mstart-1) = zeros
          mask(all other) = ones
NB (16:20) Specifies the number of bytes to move in an immediate string load or store.
OPCD (0:5) Primary op code field.
OE (21) Enables setting the OV and SO fields in the XER for extended arithmetic.
RA (11:15) Specifies a general-purpose register (GPR) to be used as a source or target.
RB (16:20) Specifies a GPR to be used as a source.
Rc (31) Record bit:
0
Do not set the CR.
1
Set the CR to reflect the result of the operation.

For fixed-point instructions, CR bits (0:3) are set to reflect the result as a signed quantity. Whether the result is an unsigned quantity or a bit string can be determined from the EQ bit.

For floating-point instructions, CR bits (4:7) are set to reflect Floating-Point Exception, Floating-Point Enabled Exception, Floating-Point Invalid Operation Exception, and Floating-Point Overflow Exception.
RS (6:10) Specifies a GPR to be used as a source.
RT (6:10) Specifies a GPR to be used as a target.
SA (30) SVC Absolute:
0
svc routine at address '1' || LEV || b'00000'
1
svc routine at address x'1FE0'
SH (16:20) Specifies a shift amount.
SI (16:31) Specifies a 16-bit signed integer. This is an immediate field.
SPR (11:20) Specifies an SPR for the mtspr and mfspr instructions. See the mtspr and mfspr instructions for information on the SPR encodings.
SR (11:15) Specifies one of the 16 Segment Registers. Bit 11 is ignored.
TO (6:10) Specifies the conditions on which to trap. See Fixed-Point Trap Instructions for more information on condition encodings.
TO Bit
ANDed with Condition
0
Compares less than.
1
Compares greater than.
2
Compares equal.
3
Compares logically less than.
4
Compares logically greater than.
U (16:19) Used as the data to be placed into the FPSCR. This is an immediate field.
UI (16:31) Specifies a 16-bit unsigned integer. This is an immediate field.
XO (21:30, 22:30, 26:30, or 30) Extended op code field.